== Ports ===========================================================
data in: in
+percolate up: root_in_r 1
+percolate down: root_in_a 1
+percolate up: root_in_d 8
+percolate down: uart_in 1
+percolate up: uart_out 1
+percolate up: uart_rts 1
+percolate down: uart_cts 1
+percolate up: rst_out 1
+percolate down: rst_in 1
+
== Constants ========================================================
== TeX ==============================================================
-\begin{verbatim}
-TODO: have some way to log multiple separate streams; use sibling
- ports to deliver an opcode
+This ship is used for debugging. It has only one port, {\tt in}.
+Programmers should send debug report values to this port. How such
+values are reported back to the programmer doing the debugging is left
+unspecified.
+
+\subsection*{To Do}
-TODO: have a way to programmatically read back the output of the debug
- ship?
+Provide an {\tt inOp} port and use opcode ports \cite{am25} to
+effectively allow multiple independent ``debug streams''
-\end{verbatim}
+Provide a way to programmatically read back the output of the debug
+ship.
== Fleeterpreter ====================================================
public void service() {
== FleetSim ==============================================================
== FPGA ==============================================================
-`include "macros.v"
-module debug (clk, data_debug_data_r, data_debug_data_a, data_debug_data,
- data_debug_out_r, data_debug_out_a, data_debug_out );
- input clk;
+ wire break_i;
+ reg break_last;
+ reg send_k; initial send_k = 0;
+
+ wire data_to_host_full;
+ wire data_to_host_write_enable;
+ wire [7:0] data_to_host;
+
+ wire data_to_fleet_empty;
+ wire data_to_fleet_read_enable;
+ wire [7:0] data_to_fleet;
+
+ reg we;
+ reg re;
+ reg [7:0] data_to_host_r;
+ assign data_to_host = data_to_host_r;
+
+ wire ser_rst;
+ reg ser_rst_r;
+ initial ser_rst_r = 0;
+ assign ser_rst = (rst_in & ser_rst_r);
+
+ wire sio_ce;
+ wire sio_ce_x4;
+
+ wire break;
+ assign rst_out = rst_in && !break;
+
+ sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4);
+ sasc_top sasc_top(clk, ser_rst,
+ uart_in,
+ uart_out,
+ uart_cts,
+ uart_rts,
+ sio_ce,
+ sio_ce_x4,
+ data_to_host,
+ data_to_fleet,
+ data_to_fleet_read_enable,
+ data_to_host_write_enable,
+ data_to_host_full,
+ data_to_fleet_empty,
+ break,
+ break_i);
+
+ // break and break are _active high_
+ always @(posedge clk) break_last <= break;
+ assign break_i = break && !break_last;
+ assign break_done = !break && break_last;
+
+ reg data_to_host_write_enable_reg;
+ reg data_to_fleet_read_enable_reg;
+
+ reg [`WORDWIDTH-1:0] root_out_d;
+ reg root_out_r; initial root_out_r = 0;
+ wire root_out_a;
+
+ reg root_out_a_reg;
+ reg root_in_r_reg;
+ reg [7:0] root_in_d_reg;
+ initial root_in_r_reg = 0;
+ initial root_in_d_reg = 0;
+ initial root_out_a_reg = 0;
+ initial data_to_fleet_read_enable_reg = 0;
+ initial data_to_host_write_enable_reg = 0;
+
+ assign root_out_a = root_out_a_reg;
+ assign root_in_r = root_in_r_reg;
+ assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
+ assign data_to_host_write_enable = data_to_host_write_enable_reg;
+ assign root_in_d = root_in_d_reg;
+
+ // fpga -> host
+ always @(posedge clk)
+ begin
+ if (break_i) begin
+ root_out_a_reg = 0;
+ data_to_host_write_enable_reg <= 0;
+
+ end else if (break_done) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= 111;
+ send_k <= 1;
+ end else if (send_k) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= 107;
+ send_k <= 0;
+
+
+ end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= root_out_d[7:0];
+ root_out_a_reg = 1;
+ end else if (root_out_a_reg && !root_out_r) begin
+ data_to_host_write_enable_reg <= 0;
+ root_out_a_reg = 0;
+ end else begin
+ data_to_host_write_enable_reg <= 0;
+ end
+ end
+
+ // host -> fpga
+ always @(posedge clk)
+ begin
+ ser_rst_r <= 1;
+ if (break_i) begin
+ root_in_r_reg <= 0;
+ root_in_d_reg <= 0;
+ data_to_fleet_read_enable_reg <= 0;
+ end else
+
+ if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
+ root_in_r_reg <= 1;
+ root_in_d_reg <= data_to_fleet;
+ data_to_fleet_read_enable_reg <= 1;
+ end else begin
+ data_to_fleet_read_enable_reg <= 0;
+ if (root_in_a) begin
+ root_in_r_reg <= 0;
+ end
+ end
+ end
+
+ reg [7:0] count;
+ initial count = 0;
- input data_debug_data_r;
- output data_debug_data_a;
- input [`DATAWIDTH:0] data_debug_data;
+ always @(posedge clk) begin
+ if (!rst) begin
+ `reset
+ end else begin
+ `flush
+ `cleanup
+ if (root_out_r && root_out_a) root_out_r <= 0;
+ if (`in_full && !root_out_r && !root_out_a && count==0) begin
+ `drain_in
+ root_out_d <= in_d;
+ root_out_r <= 1;
+ count <= 5;
+ end
+ if (count!=0 && !root_out_r && !root_out_a) begin
+ count <= count-1;
+ root_out_r <= 1;
+ root_out_d <= (root_out_d >> 8);
+ end
+ end
+ end
- output data_debug_out_r;
- input data_debug_out_a;
- output [`DATAWIDTH:0] data_debug_out;
+== Test ================================================================
+#expect 25
- assign data_debug_out_r = data_debug_data_r;
- assign data_debug_data_a = data_debug_out_a;
- assign data_debug_out = data_debug_data;
+#ship debug : Debug
-endmodule
+debug.in:
+ set word= 25;
+ deliver;
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
projects / fleet.git / blobdiff