== FPGA ==============================================================
- assign out_d_ = in_d;
- assign out_r_ = in_r;
+ reg [`DATAWIDTH-1:0] out_d;
+ assign out_d_ = out_d;
always @(posedge clk) begin
if (!rst) begin
`reset
end else begin
`flush
- in_a <= out_a;
+ `cleanup
+ if (`in_full && `out_empty) begin
+ `drain_in
+ `fill_out
+ out_d <= in_d;
+ end
end
end