== FPGA ==============================================================
+/*
wire [11:0] dvi_d;
assign dvi_d0 = dvi_d[0];
assign dvi_d1 = dvi_d[1];
assign dvi_d9 = dvi_d[9];
assign dvi_d10 = dvi_d[10];
assign dvi_d11 = dvi_d[11];
+*/
+
+wire [9:0] x_coord;
+wire [9:0] y_coord;
+assign dvi_reset_b = 1;
+wire data_valid_ext;
+assign dvi_de = data_valid_ext;
+wire clk_fb;
+wire pix_clk;
+wire[7:0] dvi_green;
+wire[7:0] dvi_red;
+wire[7:0] dvi_blue;
+
+//assign dvi_green = 8'b101010;
+//assign dvi_red = 8'b111111;
+//assign dvi_blue = 8'b000000;
+
+assign dvi_green = x_coord[7:0];
+assign dvi_red = y_coord[7:0];
+assign dvi_blue = 8'b00000000;
+
+vga_timing_generator
+ #(
+ .WIDTH(640),
+ .H_FP(16),
+ .H_SYNC(96),
+ .H_BP(48),
+ .HEIGHT(480),
+ .V_FP(12),
+ .V_SYNC(2),
+ .V_BP(31),
+ .HEIGHT_BITS(10),
+ .WIDTH_BITS(10),
+ .DATA_DELAY(0)
+ ) my_vga_timing_generator (
+ .rst(rst),
+ .clk(pix_clk),
+ .hsync(dvi_h),
+ .vsync(dvi_v),
+ .X_COORD(x_coord),
+ .Y_COORD(y_coord),
+ .DATA_VALID(),
+ .DATA_VALID_EXT(data_valid_ext),
+ .PIXEL_COUNT()
+ );
+
+ ODDR #(
+ .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
+ .INIT(1'b0), // Initial value for Q port ('1' or '0')
+ .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
+ ) ODDR_xclk_p (
+ .Q(dvi_xclk_p), // 1-bit DDR output
+ .C(pix_clk), // 1-bit clock input
+ .CE(1), // 1-bit clock enable input
+ .D1(1), // 1-bit data input (positive edge)
+ .D2(0), // 1-bit data input (negative edge)
+ .R(0), // 1-bit reset input
+ .S(0) // 1-bit set input
+ );
+ ODDR #(
+ .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
+ .INIT(1'b0), // Initial value for Q port ('1' or '0')
+ .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
+ ) ODDR_xclk_n (
+ .Q(dvi_xclk_n), // 1-bit DDR output
+ .C(pix_clk), // 1-bit clock input
+ .CE(1), // 1-bit clock enable input
+ .D1(0), // 1-bit data input (positive edge)
+ .D2(1), // 1-bit data input (negative edge)
+ .R(0), // 1-bit reset input
+ .S(0) // 1-bit set input
+ );
+
+ i2c_video_programmer my_i2c_video_programmer_i (
+ .CLK200Mhz(clk),
+ .RST(rst),
+ .I2C_SDA(dvi_iic_sda),
+ .I2C_SCL(dvi_iic_scl));
+
+ DCM_BASE #(
+ .CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ .CLKFX_DIVIDE(16), // Can be any interger from 1 to 32
+ .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
+ .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
+ .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
+ .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
+ .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
+ .DCM_AUTOCALIBRATION("TRUE"), // DCM calibrartion circuitry TRUE/FALSE
+ .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
+ .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ .DFS_FREQUENCY_MODE("HIGH"), // LOW or HIGH frequency mode for frequency synthesis
+ .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
+ .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
+ .FACTORY_JF(16'hF0F0), // FACTORY JF Values Suggested to be set to X"F0F0"
+ .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
+ .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ ) DCM_BASE_dvi (
+ .CLK0(clk_fb),
+ .CLKDV(pix_clk),
+ .CLKFB(clk_fb),
+ .CLKIN(clk),
+ .RST(rst)
+ );
+
+ ODDR ODDR_dvi_d0 (dvi_d0, pix_clk, 1, dvi_green[4], dvi_blue[0], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d1 (dvi_d1, pix_clk, 1, dvi_green[5], dvi_blue[1], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d2 (dvi_d2, pix_clk, 1, dvi_green[6], dvi_blue[2], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d3 (dvi_d3, pix_clk, 1, dvi_green[7], dvi_blue[3], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d4 (dvi_d4, pix_clk, 1, dvi_red[0], dvi_blue[4], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d5 (dvi_d5, pix_clk, 1, dvi_red[1], dvi_blue[5], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d6 (dvi_d6, pix_clk, 1, dvi_red[2], dvi_blue[6], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d7 (dvi_d7, pix_clk, 1, dvi_red[3], dvi_blue[7], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d8 (dvi_d8, pix_clk, 1, dvi_red[4], dvi_green[0], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d9 (dvi_d9, pix_clk, 1, dvi_red[5], dvi_green[1], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d10 (dvi_d10, pix_clk, 1, dvi_red[6], dvi_green[2], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d11 (dvi_d11, pix_clk, 1, dvi_red[7], dvi_green[3], ~data_valid_ext, 0);
+
+
+/*
dvi_video_test my_dvi_video_test(
.CLK_P(clk),
.CLK_N(clk),
- .I2C_SDA(dvi_iic_sda),
- .I2C_SCL(dvi_iic_scl),
.DVI_D(dvi_d),
.DVI_H(dvi_h),
.DVI_DATA_VALID()
);
-
+*/
/*
projects / fleet.git / blobdiff