-ship: Video
+ship: Dvi
== Ports ===========================================================
-data in: inX
-data in: inY
-data in: inData
+data in: inPixelX
+data in: inPixelY
+data in: inPixelValue
+
+data in: inAddrRead
+data in: inAddrWrite
+data in: inDataWrite
+
+data out: out
percolate up: dvi_d0 1
percolate up: dvi_d1 1
percolate up: dvi_de 1
percolate up: dvi_reset_b 1
-percolate up: gpio_led_c 1
-percolate up: gpio_led_e 1
-percolate up: gpio_led_n 1
-percolate up: gpio_led_s 1
-percolate up: gpio_led_w 1
percolate up: gpio_led_4 1
percolate up: gpio_led_5 1
percolate up: gpio_led_6 1
percolate up: gpio_led_7 1
-== TeX ==============================================================
-
-== Fleeterpreter ====================================================
-//percolate down: dvi_gpio1 1
-//percolate up: dvi_iic_scl 1
-//percolate inout: dvi_iic_sda 1
-
- public void service() { }
-
-== FleetSim ==============================================================
+percolate up: dvi_iic_scl 1
+percolate inout: dvi_iic_sda 1
+
+percolate up: gpio_led_0 1
+percolate up: gpio_led_1 1
+percolate up: gpio_led_2 1
+percolate up: gpio_led_3 1
+
+percolate up: sram_adv_ld_b 1
+percolate up: sram_bw0 1
+percolate up: sram_bw1 1
+percolate up: sram_bw2 1
+percolate up: sram_bw3 1
+percolate up: sram_clk 1
+percolate up: sram_cs_b 1
+percolate up: sram_flash_a0 1
+percolate up: sram_flash_a1 1
+percolate up: sram_flash_a2 1
+percolate up: sram_flash_a3 1
+percolate up: sram_flash_a4 1
+percolate up: sram_flash_a5 1
+percolate up: sram_flash_a6 1
+percolate up: sram_flash_a7 1
+percolate up: sram_flash_a8 1
+percolate up: sram_flash_a9 1
+percolate up: sram_flash_a10 1
+percolate up: sram_flash_a11 1
+percolate up: sram_flash_a12 1
+percolate up: sram_flash_a13 1
+percolate up: sram_flash_a14 1
+percolate up: sram_flash_a15 1
+percolate up: sram_flash_a16 1
+percolate up: sram_flash_a17 1
+percolate up: sram_flash_a18 1
+percolate up: sram_flash_a19 1
+percolate up: sram_flash_a20 1
+percolate up: sram_flash_a21 1
+percolate up: sram_flash_we_b 1
+percolate up: sram_mode 1
+percolate up: sram_oe_b 1
+
+percolate inout: sram_dqp0 1
+percolate inout: sram_dqp1 1
+percolate inout: sram_dqp2 1
+percolate inout: sram_dqp3 1
+
+percolate inout: sram_flash_d0 1
+percolate inout: sram_flash_d1 1
+percolate inout: sram_flash_d2 1
+percolate inout: sram_flash_d3 1
+percolate inout: sram_flash_d4 1
+percolate inout: sram_flash_d5 1
+percolate inout: sram_flash_d6 1
+percolate inout: sram_flash_d7 1
+percolate inout: sram_flash_d8 1
+percolate inout: sram_flash_d9 1
+percolate inout: sram_flash_d10 1
+percolate inout: sram_flash_d11 1
+percolate inout: sram_flash_d12 1
+percolate inout: sram_flash_d13 1
+percolate inout: sram_flash_d14 1
+percolate inout: sram_flash_d15 1
+percolate inout: sram_d16 1
+percolate inout: sram_d17 1
+percolate inout: sram_d18 1
+percolate inout: sram_d19 1
+percolate inout: sram_d20 1
+percolate inout: sram_d21 1
+percolate inout: sram_d22 1
+percolate inout: sram_d23 1
+percolate inout: sram_d24 1
+percolate inout: sram_d25 1
+percolate inout: sram_d26 1
+percolate inout: sram_d27 1
+percolate inout: sram_d28 1
+percolate inout: sram_d29 1
+percolate inout: sram_d30 1
+percolate inout: sram_d31 1
== FPGA ==============================================================
- assign dvi_de = 1;
- assign dvi_reset_b = 1;
-
- assign dvi_d0 = 1;
- assign dvi_d1 = 0;
- assign dvi_d2 = 1;
- assign dvi_d3 = 0;
- assign dvi_d4 = 1;
- assign dvi_d5 = 0;
- assign dvi_d6 = 1;
- assign dvi_d7 = 0;
- assign dvi_d8 = 1;
- assign dvi_d9 = 0;
- assign dvi_d10 = 1;
- assign dvi_d11 = 0;
-
- assign gpio_led_n = 1;
- assign gpio_led_s = 0;
-
-// assign gpio_led_0 = dvi_gpio1;
-// assign gpio_led_1 = 0;
-// assign gpio_led_2 = 1;
-// assign gpio_led_3 = 0;
-// assign gpio_led_4 = 1;
- assign gpio_led_5 = 0;
- assign gpio_led_6 = 1;
- assign gpio_led_7 = 0;
-
- wire dvi_xclk_p_unbuffered;
- wire dvi_xclk_n_unbuffered;
- wire dvi_xclk_fb;
-
-/*
- BUFG GBUF_FOR_DVI_CLOCK_N (.I(dvi_xclk_n_unbuffered), .O(dvi_xclk_n));
- BUFG GBUF_FOR_DVI_CLOCK_P (.I(dvi_xclk_p_unbuffered), .O(dvi_xclk_p));
- DCM // 25Mhz VGA clock
- #(
- .CLKFX_MULTIPLY(4),
- .CLKFX_DIVIDE(16),
- .CLKIN_PERIOD("20 ns")
- ) vgadcm (
- .CLKIN (clk),
- .CLKFB (dvi_xclk_fb),
- .CLKFX (dvi_xclk_p_unbuffered),
- .CLKFX180 (dvi_xclk_n_unbuffered),
- .CLK0 (dvi_xclk_fb)
- );
-*/
-
- wire [31:0] vga_pixel_addr_;
- wire vga_pixel_r;
- wire vga_pixel_a_;
- reg vga_pixel_a;
- assign vga_pixel_a_ = vga_pixel_a;
- wire [18:0] inAddr;
+wire [9:0] x_coord;
+wire [9:0] y_coord;
+wire data_valid_ext;
+wire clk_fb;
+wire pix_clk;
+wire[7:0] dvi_green;
+wire[7:0] dvi_red;
+wire[7:0] dvi_blue;
+
+assign dvi_reset_b = 1;
+assign dvi_de = data_valid_ext;
+
+vga_timing_generator
+ #(
+ .WIDTH(640),
+ .H_FP(16),
+ .H_SYNC(96),
+ .H_BP(48),
+ .HEIGHT(480),
+ .V_FP(12),
+ .V_SYNC(2),
+ .V_BP(31),
+ .HEIGHT_BITS(10),
+ .WIDTH_BITS(10),
+ .DATA_DELAY(0)
+ ) my_vga_timing_generator (
+ .rst(rst),
+ .clk(pix_clk),
+ .hsync(dvi_h),
+ .vsync(dvi_v),
+ .X_COORD(x_coord),
+ .Y_COORD(y_coord),
+ .DATA_VALID(),
+ .DATA_VALID_EXT(data_valid_ext),
+ .PIXEL_COUNT()
+ );
+
+ ODDR #(
+ .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
+ .INIT(1'b0), // Initial value for Q port ('1' or '0')
+ .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
+ ) ODDR_xclk_p (
+ .Q(dvi_xclk_p), // 1-bit DDR output
+ .C(pix_clk), // 1-bit clock input
+ .CE(1), // 1-bit clock enable input
+ .D1(1), // 1-bit data input (positive edge)
+ .D2(0), // 1-bit data input (negative edge)
+ .R(0), // 1-bit reset input
+ .S(0) // 1-bit set input
+ );
+ ODDR #(
+ .DDR_CLK_EDGE("OPPOSITE_EDGE"), // "OPPOSITE_EDGE" or "SAME_EDGE"
+ .INIT(1'b0), // Initial value for Q port ('1' or '0')
+ .SRTYPE("SYNC") // Reset Type ("ASYNC" or "SYNC")
+ ) ODDR_xclk_n (
+ .Q(dvi_xclk_n), // 1-bit DDR output
+ .C(pix_clk), // 1-bit clock input
+ .CE(1), // 1-bit clock enable input
+ .D1(0), // 1-bit data input (positive edge)
+ .D2(1), // 1-bit data input (negative edge)
+ .R(0), // 1-bit reset input
+ .S(0) // 1-bit set input
+ );
+
+ i2c_video_programmer my_i2c_video_programmer_i (
+ .CLK200Mhz(clk),
+ .RST(rst),
+ .I2C_SDA(dvi_iic_sda),
+ .I2C_SCL(dvi_iic_scl));
+
+ DCM_BASE #(
+ .CLKDV_DIVIDE(4.0), // Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
+ .CLKFX_DIVIDE(16), // Can be any interger from 1 to 32
+ .CLKFX_MULTIPLY(2), // Can be any integer from 2 to 32
+ .CLKIN_DIVIDE_BY_2("FALSE"), // TRUE/FALSE to enable CLKIN divide by two feature
+ .CLKIN_PERIOD(10.0), // Specify period of input clock in ns from 1.25 to 1000.00
+ .CLKOUT_PHASE_SHIFT("NONE"), // Specify phase shift mode of NONE or FIXED
+ .CLK_FEEDBACK("1X"), // Specify clock feedback of NONE or 1X
+ .DCM_AUTOCALIBRATION("TRUE"), // DCM calibrartion circuitry TRUE/FALSE
+ .DCM_PERFORMANCE_MODE("MAX_SPEED"), // Can be MAX_SPEED or MAX_RANGE
+ .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"), // SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or
+ .DFS_FREQUENCY_MODE("HIGH"), // LOW or HIGH frequency mode for frequency synthesis
+ .DLL_FREQUENCY_MODE("LOW"), // LOW, HIGH, or HIGH_SER frequency mode for DLL
+ .DUTY_CYCLE_CORRECTION("TRUE"), // Duty cycle correction, TRUE or FALSE
+ .FACTORY_JF(16'hF0F0), // FACTORY JF Values Suggested to be set to X"F0F0"
+ .PHASE_SHIFT(0), // Amount of fixed phase shift from -255 to 1023
+ .STARTUP_WAIT("FALSE") // Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ ) DCM_BASE_dvi (
+ .CLK0(clk_fb),
+ .CLKDV(pix_clk),
+ .CLKFB(clk_fb),
+ .CLKIN(clk),
+ .RST(rst)
+ );
+
+ ODDR ODDR_dvi_d0 (dvi_d0, pix_clk, 1, dvi_green[4], dvi_blue[0], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d1 (dvi_d1, pix_clk, 1, dvi_green[5], dvi_blue[1], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d2 (dvi_d2, pix_clk, 1, dvi_green[6], dvi_blue[2], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d3 (dvi_d3, pix_clk, 1, dvi_green[7], dvi_blue[3], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d4 (dvi_d4, pix_clk, 1, dvi_red[0], dvi_blue[4], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d5 (dvi_d5, pix_clk, 1, dvi_red[1], dvi_blue[5], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d6 (dvi_d6, pix_clk, 1, dvi_red[2], dvi_blue[6], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d7 (dvi_d7, pix_clk, 1, dvi_red[3], dvi_blue[7], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d8 (dvi_d8, pix_clk, 1, dvi_red[4], dvi_green[0], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d9 (dvi_d9, pix_clk, 1, dvi_red[5], dvi_green[1], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d10 (dvi_d10, pix_clk, 1, dvi_red[6], dvi_green[2], ~data_valid_ext, 0);
+ ODDR ODDR_dvi_d11 (dvi_d11, pix_clk, 1, dvi_red[7], dvi_green[3], ~data_valid_ext, 0);
reg we;
- wire [2:0] mem_out;
- wire [31:0] vga_pixel_data;
- assign vga_pixel_data = {
- 8'b0,
- mem_out[2], 7'b0,
- mem_out[1], 7'b0,
- mem_out[0], 7'b0
- };
-
- assign inAddr = inX_d + (inY_d * 640);
-
- vram vram(clk, !rst, we, inAddr[18:0], vga_pixel_addr_[20:2], inData_d, , mem_out);
-
- wb_vga wb_vga(
- .wb_clk_i(clk),
- .wb_rst_i(rst),
-
- .fbwb_adr_o(vga_pixel_addr_),
- .fbwb_stb_o(vga_pixel_r),
- .fbwb_ack_i(vga_pixel_a_),
- .fbwb_dat_i(vga_pixel_data),
-
- /* VGA signals */
- .vga_clk(dvi_xclk),
- .vga_psave(vga_psave),
- .vga_hsync(dvi_h),
- .vga_vsync(dvi_v),
- .vga_sync(vga_sync),
- .vga_blank(vga_blank),
- .vga_r(vga_r),
- .vga_g(vga_g),
- .vga_b(vga_b)
- // .vga_clkout(vga_clkout)
- );
+ reg [31:0] mem_out;
+ wire [20:0] inAddr;
+ wire [20:0] vga_pixel_addr_;
+ reg [20:0] vga_pixel_addr;
+ reg [20:0] last_vga_pixel_addr;
+
+ reg write_enable;
+ reg oe;
+ reg [3:0] wait_until_read;
+ reg [3:0] wait_until_write;
+ reg [3:0] wait_until_video;
+ reg [37:0] addr;
+ wire [35:0] data_out;
+ reg [37:0] out_d;
+ reg [37:0] writeData;
+
+ reg use_addr;
+
+ assign out_d_ = out_d;
+
+ assign sram_flash_a0 = use_addr ? addr[0] : 0;
+ assign sram_flash_a1 = use_addr ? addr[1] : vga_pixel_addr[0];
+ assign sram_flash_a2 = use_addr ? addr[2] : vga_pixel_addr[1];
+ assign sram_flash_a3 = use_addr ? addr[3] : vga_pixel_addr[2];
+ assign sram_flash_a4 = use_addr ? addr[4] : vga_pixel_addr[3];
+ assign sram_flash_a5 = use_addr ? addr[5] : vga_pixel_addr[4];
+ assign sram_flash_a6 = use_addr ? addr[6] : vga_pixel_addr[5];
+ assign sram_flash_a7 = use_addr ? addr[7] : vga_pixel_addr[6];
+ assign sram_flash_a8 = use_addr ? addr[8] : vga_pixel_addr[7];
+ assign sram_flash_a9 = use_addr ? addr[9] : vga_pixel_addr[8];
+ assign sram_flash_a10 = use_addr ? addr[10] : vga_pixel_addr[9];
+ assign sram_flash_a11 = use_addr ? addr[11] : vga_pixel_addr[10];
+ assign sram_flash_a12 = use_addr ? addr[12] : vga_pixel_addr[11];
+ assign sram_flash_a13 = use_addr ? addr[13] : vga_pixel_addr[12];
+ assign sram_flash_a14 = use_addr ? addr[14] : vga_pixel_addr[13];
+ assign sram_flash_a15 = use_addr ? addr[15] : vga_pixel_addr[14];
+ assign sram_flash_a16 = use_addr ? addr[16] : vga_pixel_addr[15];
+ assign sram_flash_a17 = use_addr ? addr[17] : vga_pixel_addr[16];
+ assign sram_flash_a18 = use_addr ? addr[18] : vga_pixel_addr[17];
+ assign sram_flash_a19 = use_addr ? addr[19] : vga_pixel_addr[18];
+ assign sram_flash_a20 = use_addr ? addr[20] : vga_pixel_addr[19];
+ assign sram_flash_a21 = use_addr ? addr[21] : vga_pixel_addr[20];
+
+ assign data_out[0] = sram_flash_d0; assign sram_flash_d0 = oe ? 1'bz : writeData[0];
+ assign data_out[1] = sram_flash_d1; assign sram_flash_d1 = oe ? 1'bz : writeData[1];
+ assign data_out[2] = sram_flash_d2; assign sram_flash_d2 = oe ? 1'bz : writeData[2];
+ assign data_out[3] = sram_flash_d3; assign sram_flash_d3 = oe ? 1'bz : writeData[3];
+ assign data_out[4] = sram_flash_d4; assign sram_flash_d4 = oe ? 1'bz : writeData[4];
+ assign data_out[5] = sram_flash_d5; assign sram_flash_d5 = oe ? 1'bz : writeData[5];
+ assign data_out[6] = sram_flash_d6; assign sram_flash_d6 = oe ? 1'bz : writeData[6];
+ assign data_out[7] = sram_flash_d7; assign sram_flash_d7 = oe ? 1'bz : writeData[7];
+ assign data_out[8] = sram_flash_d8; assign sram_flash_d8 = oe ? 1'bz : writeData[8];
+ assign data_out[9] = sram_flash_d9; assign sram_flash_d9 = oe ? 1'bz : writeData[9];
+ assign data_out[10] = sram_flash_d10; assign sram_flash_d10 = oe ? 1'bz : writeData[10];
+ assign data_out[11] = sram_flash_d11; assign sram_flash_d11 = oe ? 1'bz : writeData[11];
+ assign data_out[12] = sram_flash_d12; assign sram_flash_d12 = oe ? 1'bz : writeData[12];
+ assign data_out[13] = sram_flash_d13; assign sram_flash_d13 = oe ? 1'bz : writeData[13];
+ assign data_out[14] = sram_flash_d14; assign sram_flash_d14 = oe ? 1'bz : writeData[14];
+ assign data_out[15] = sram_flash_d15; assign sram_flash_d15 = oe ? 1'bz : writeData[15];
+ assign data_out[16] = sram_d16; assign sram_d16 = oe ? 1'bz : writeData[16];
+ assign data_out[17] = sram_d17; assign sram_d17 = oe ? 1'bz : writeData[17];
+ assign data_out[18] = sram_d18; assign sram_d18 = oe ? 1'bz : writeData[18];
+ assign data_out[19] = sram_d19; assign sram_d19 = oe ? 1'bz : writeData[19];
+ assign data_out[20] = sram_d20; assign sram_d20 = oe ? 1'bz : writeData[20];
+ assign data_out[21] = sram_d21; assign sram_d21 = oe ? 1'bz : writeData[21];
+ assign data_out[22] = sram_d22; assign sram_d22 = oe ? 1'bz : writeData[22];
+ assign data_out[23] = sram_d23; assign sram_d23 = oe ? 1'bz : writeData[23];
+ assign data_out[24] = sram_d24; assign sram_d24 = oe ? 1'bz : writeData[24];
+ assign data_out[25] = sram_d25; assign sram_d25 = oe ? 1'bz : writeData[25];
+ assign data_out[26] = sram_d26; assign sram_d26 = oe ? 1'bz : writeData[26];
+ assign data_out[27] = sram_d27; assign sram_d27 = oe ? 1'bz : writeData[27];
+ assign data_out[28] = sram_d28; assign sram_d28 = oe ? 1'bz : writeData[28];
+ assign data_out[29] = sram_d29; assign sram_d29 = oe ? 1'bz : writeData[29];
+ assign data_out[30] = sram_d30; assign sram_d30 = oe ? 1'bz : writeData[30];
+ assign data_out[31] = sram_d31; assign sram_d31 = oe ? 1'bz : writeData[31];
+ assign data_out[32] = sram_dqp0; assign sram_dqp0 = oe ? 1'bz : writeData[32];
+ assign data_out[33] = sram_dqp1; assign sram_dqp1 = oe ? 1'bz : writeData[33];
+ assign data_out[34] = sram_dqp2; assign sram_dqp2 = oe ? 1'bz : writeData[34];
+ assign data_out[35] = sram_dqp3; assign sram_dqp3 = oe ? 1'bz : writeData[35];
+
+ assign sram_mode = 0;
+ assign sram_clk = clk;
+ assign sram_bw0 = ~write_enable;
+ assign sram_bw1 = ~write_enable;
+ assign sram_bw2 = ~write_enable;
+ assign sram_bw3 = ~write_enable;
+ assign sram_flash_we_b = ~write_enable;
+ assign sram_adv_ld_b = 0;
+ assign sram_cs_b = 0;
+ assign sram_oe_b = ~oe;
+
+ // Framebuffer is 544x478 -- yeah, I know that's completely weird.
+
+ wire on_screen_;
+ reg on_screen;
+ assign on_screen_ = (x_coord >= 48) && (x_coord < 592);
+ wire [9:0] adjusted_x_coord;
+ assign adjusted_x_coord = x_coord - 48;
+
+ assign inAddr = inPixelX_d[20:0]
+ + { 7'b0000000, inPixelY_d[8:0], 5'b00000 }
+ + { 3'b000, inPixelY_d[8:0], 9'b0000000000 };
+ assign vga_pixel_addr_ = { 11'b00000000000, adjusted_x_coord }
+ + { 7'b0000000, y_coord[8:0], 5'b00000 }
+ + { 3'b000, y_coord[8:0], 9'b0000000000 };
+
+ assign dvi_red = on_screen ? { mem_out[17:12], 2'b0 } : 0;
+ assign dvi_green = on_screen ? { mem_out[11:6], 2'b0 } : 0;
+ assign dvi_blue = on_screen ? { mem_out[5:0], 2'b0 } : 0;
+
+ always @(posedge pix_clk) begin
+ vga_pixel_addr <= vga_pixel_addr_;
+ on_screen <= on_screen_;
+ end
- always @(posedge clk) begin
+ wire idle;
+ assign idle = (wait_until_write==0 && wait_until_read==0 && wait_until_video==0);
+ always @(posedge clk) begin
if (rst) begin
`reset
+ wait_until_read <= 0;
+ wait_until_video <= 0;
+ wait_until_write <= 0;
+ use_addr <= 0;
+
end else begin
`cleanup
- vga_pixel_a <= vga_pixel_r;
-
- if (`inX_full && `inY_full && `inData_full) begin
- we <= 1;
- `drain_inX
- `drain_inY
- `drain_inData
- end else begin
- we <= 0;
+
+ write_enable <= 0;
+ oe <= 1;
+
+ if (wait_until_write == 1) begin
+ wait_until_write <= 0;
+ oe <= 0;
+ use_addr <= 0;
+ end else if (wait_until_write != 0) begin
+ wait_until_write <= wait_until_write-1;
end
+ if (wait_until_read == 1) begin
+ wait_until_read <= 0;
+ out_d <= { 1'b0, data_out };
+ `fill_out
+ `drain_inAddrRead
+ use_addr <= 0;
+ end else if (wait_until_read != 0) begin
+ wait_until_read <= wait_until_read-1;
+ end
+
+ if (wait_until_video == 1) begin
+ wait_until_video <= 0;
+ mem_out <= data_out;
+ end else if (wait_until_video != 0) begin
+ wait_until_video <= wait_until_video-1;
+ end
+
+ if (`inAddrWrite_full && `inDataWrite_full && idle && `out_empty) begin
+ write_enable <= 1;
+ wait_until_write <= 1;
+ addr <= { inAddrWrite_d, 1'b0 };
+ writeData <= inDataWrite_d;
+ out_d <= { 1'b1, 37'b0 };
+ use_addr <= 1;
+ `fill_out
+ `drain_inDataWrite
+ `drain_inAddrWrite
+
+ end else if (`inPixelX_full && `inPixelY_full && `inPixelValue_full && idle) begin
+ `drain_inPixelX
+ `drain_inPixelY
+ `drain_inPixelValue
+ write_enable <= 1;
+ wait_until_write <= 1;
+ addr <= { inAddr, 1'b0 };
+ writeData <= inPixelValue_d;
+ use_addr <= 1;
+
+ end else if (`inAddrRead_full && idle && `out_empty) begin
+ // next cycle (wait_until_read==3) will assert the address for the request
+ // cycle after that (wait_until_read==2) is the gap
+ // cycle after that (wait_until_read==1) will have the valid data being asserted back
+ // unfortunately, I seem to get errors unless I wait for an EXTRA cycle on top of this.
+// wait_until_read <= 3;
+ wait_until_read <= 4;
+ addr <= { inAddrRead_d, 1'b0 };
+ use_addr <= 1;
+
+ end else if (last_vga_pixel_addr != vga_pixel_addr && idle && on_screen) begin
+ // wait_until_video can't be more than 3, because (3+1) is the ratio of the pixel clock to the host clock
+ wait_until_video <= 3;
+ addr <= { vga_pixel_addr, 1'b0 };
+ last_vga_pixel_addr <= vga_pixel_addr;
+
+ end
+
end
end
-*/
== UCF ===============================================================
NET dvi_iic_scl LOC="U27" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
NET dvi_iic_sda LOC="T29" | PULLUP | IOSTANDARD="LVCMOS18"; # Bank 15, Vcco=1.8V, DCI using 49.9 ohm resistors
-NET gpio_sw_c LOC="AJ6" | IOSTANDARD="LVCMOS33"; # Bank 18, Vcco=3.3V, No DCI
-
-NET gpio_led_c LOC="E8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
-NET gpio_led_e LOC="AG23"; # Bank 2, Vcco=3.3V
-NET gpio_led_n LOC="AF13"; # Bank 2, Vcco=3.3V
-NET gpio_led_s LOC="AG12"; # Bank 2, Vcco=3.3V
-NET gpio_led_w LOC="AF23"; # Bank 2, Vcco=3.3V
-
NET gpio_led_0 LOC="H18"; # Bank 3, Vcco=2.5V, No DCI
NET gpio_led_1 LOC="L18"; # Bank 3, Vcco=2.5V, No DCI
NET gpio_led_2 LOC="G15"; # Bank 3, Vcco=2.5V, No DCI
NET gpio_led_6 LOC="AD24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
NET gpio_led_7 LOC="AE24" | IOSTANDARD="LVCMOS18"; # Bank 21, Vcco=1.8V, DCI using 49.9 ohm resistors
+######
+
+NET sram_adv_ld_b LOC="H8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw0 LOC="D10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw1 LOC="D11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw2 LOC="J11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_bw3 LOC="K11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_clk LOC="AG21"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_clk LOC="G8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_cs_b LOC="J10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d16 LOC="N10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d17 LOC="E13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d18 LOC="E12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d19 LOC="L9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d20 LOC="M10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d21 LOC="E11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d22 LOC="F11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d23 LOC="L8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d24 LOC="M8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d25 LOC="G12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d26 LOC="G11"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d27 LOC="C13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d28 LOC="B13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d29 LOC="K9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d30 LOC="K8"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_d31 LOC="J9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp0 LOC="D12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp1 LOC="C12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp2 LOC="H10"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_dqp3 LOC="H9"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_flash_a0 LOC="K12"; # Bank 1, Vcco=3.3V
+NET sram_flash_a1 LOC="K13"; # Bank 1, Vcco=3.3V
+NET sram_flash_a2 LOC="H23"; # Bank 1, Vcco=3.3V
+NET sram_flash_a3 LOC="G23"; # Bank 1, Vcco=3.3V
+NET sram_flash_a4 LOC="H12"; # Bank 1, Vcco=3.3V
+NET sram_flash_a5 LOC="J12"; # Bank 1, Vcco=3.3V
+NET sram_flash_a6 LOC="K22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a7 LOC="K23"; # Bank 1, Vcco=3.3V
+NET sram_flash_a8 LOC="K14"; # Bank 1, Vcco=3.3V
+NET sram_flash_a9 LOC="L14"; # Bank 1, Vcco=3.3V
+NET sram_flash_a10 LOC="H22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a11 LOC="G22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a12 LOC="J15"; # Bank 1, Vcco=3.3V
+NET sram_flash_a13 LOC="K16"; # Bank 1, Vcco=3.3V
+NET sram_flash_a14 LOC="K21"; # Bank 1, Vcco=3.3V
+NET sram_flash_a15 LOC="J22"; # Bank 1, Vcco=3.3V
+NET sram_flash_a16 LOC="L16"; # Bank 1, Vcco=3.3V
+NET sram_flash_a17 LOC="L15"; # Bank 1, Vcco=3.3V
+NET sram_flash_a18 LOC="L20"; # Bank 1, Vcco=3.3V
+NET sram_flash_a19 LOC="L21"; # Bank 1, Vcco=3.3V
+NET sram_flash_a20 LOC="AE23"; # Bank 2, Vcco=3.3V
+NET sram_flash_a21 LOC="AE22"; # Bank 2, Vcco=3.3V
+NET sram_flash_d0 LOC="AD19"; # Bank 2, Vcco=3.3V
+NET sram_flash_d1 LOC="AE19"; # Bank 2, Vcco=3.3V
+NET sram_flash_d2 LOC="AE17"; # Bank 2, Vcco=3.3V
+NET sram_flash_d3 LOC="AF16"; # Bank 2, Vcco=3.3V
+NET sram_flash_d4 LOC="AD20"; # Bank 2, Vcco=3.3V
+NET sram_flash_d5 LOC="AE21"; # Bank 2, Vcco=3.3V
+NET sram_flash_d6 LOC="AE16"; # Bank 2, Vcco=3.3V
+NET sram_flash_d7 LOC="AF15"; # Bank 2, Vcco=3.3V
+NET sram_flash_d8 LOC="AH13"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d9 LOC="AH14"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d10 LOC="AH19"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d11 LOC="AH20"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d12 LOC="AG13"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d13 LOC="AH12"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d14 LOC="AH22"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_d15 LOC="AG22"; # Bank 4, Vcco=3.3V, No DCI
+NET sram_flash_we_b LOC="AF20"; # Bank 2, Vcco=3.3V
+NET sram_mode LOC="A13"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+NET sram_oe_b LOC="B12"; # Bank 20, Vcco=3.3V, DCI using 49.9 ohm resistors
+
+
+
== TeX ==============================================================
== Fleeterpreter ====================================================
-
- public void service() { }
+private java.awt.Frame frame = null;
+private java.awt.Panel panel = null;
+private long[][] bits;
+public static int SCREEN_WIDTH = 577;
+public static int SCREEN_HEIGHT = 478;
+public void service() {
+ long x,y,d;
+ if (box_inPixelX.dataReadyForShip() &&
+ box_inPixelY.dataReadyForShip() &&
+ box_inPixelValue.dataReadyForShip()) {
+ x = box_inPixelX.removeDataForShip();
+ y = box_inPixelY.removeDataForShip();
+ d = box_inPixelValue.removeDataForShip();
+ } else if (box_inAddrWrite.dataReadyForShip() &&
+ box_inDataWrite.dataReadyForShip() &&
+ box_out.readyForDataFromShip()) {
+ long addr = box_inAddrWrite.removeDataForShip();
+ x = addr % SCREEN_WIDTH;
+ y = addr / SCREEN_WIDTH;
+ d = box_inDataWrite.removeDataForShip();
+ box_out.addDataFromShip(0,true);
+ } else if (box_inAddrRead.dataReadyForShip() &&
+ box_out.readyForDataFromShip()) {
+ long addr = box_inAddrRead.removeDataForShip();
+ x = addr % SCREEN_WIDTH;
+ y = addr / SCREEN_WIDTH;
+ box_out.addDataFromShip(bits[(int)x][(int)y],false);
+ return;
+ } else {
+ return;
+ }
+ if (frame==null) {
+ frame = new java.awt.Frame();
+ bits = new long[SCREEN_WIDTH][SCREEN_HEIGHT];
+ for(int i=0; i<SCREEN_WIDTH; i++) bits[i] = new long[SCREEN_HEIGHT];
+ frame.setSize(SCREEN_WIDTH,SCREEN_HEIGHT);
+ panel = new java.awt.Panel() {
+ public void paint(java.awt.Graphics g_) {
+ java.awt.Graphics2D g2 = (java.awt.Graphics2D)g_;
+ g2.transform(java.awt.geom.AffineTransform.getScaleInstance(((double)panel.getWidth())/SCREEN_WIDTH,
+ ((double)panel.getHeight())/SCREEN_HEIGHT));
+ for(int xx=0; xx<SCREEN_WIDTH; xx++) {
+ for(int yy=0; yy<SCREEN_HEIGHT; yy++) {
+ long d = bits[xx][yy];
+ java.awt.Color c = new java.awt.Color(
+ (int)(((d >> 12) & ~((-1L) << 6)) << 2),
+ (int)(((d >> 6) & ~((-1L) << 6)) << 2),
+ (int)(((d >> 0) & ~((-1L) << 6)) << 2)
+ );
+ g2.setColor(c);
+ g2.fillRect((int)xx,(int)yy,1,1);
+ }
+ }
+ }
+ };
+ frame.setLayout(new java.awt.BorderLayout());
+ frame.add(panel, java.awt.BorderLayout.CENTER);
+ panel.setBackground(java.awt.Color.black);
+ frame.show();
+ }
+ bits[(int)x][(int)y] = d;
+ panel.repaint();
+}
== FleetSim ==============================================================
== Test ==============================================================
#skip
+#expect 0
+#expect 0
+#expect 0
+
#ship debug : Debug
+#ship video : Dvi
+
+video.inPixelX:
+ set word=0;
+ deliver;
+ send token to debug.in;
+video.inPixelY:
+ set word=0;
+ deliver;
+ send token to debug.in;
+video.inPixelValue:
+ set word=0;
+ deliver;
+ send token to debug.in;
+
+debug.in:
+ set word=0;
+ set ilc=*;
+ recv token, deliver;
+
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>
projects / fleet.git / blobdiff