factor out verilog headers on Alu2 ship

[fleet.git] / ships / Execute.ship

diff --git a/ships/Execute.ship b/ships/Execute.ship
index 4fe66a4..5fd49d0 100644 (file)
--- a/ships/Execute.ship
+++ b/ships/Execute.ship
@@ -14,17 +14,17 @@ data  in:   in
 == FPGA ==============================================================
 `include "macros.v"
 
-module execute (clk, command_r,   command_a_, command_d,
+module execute (clk, in_r,     in_a_,   in_d,
                      ihorn_r_, ihorn_a, ihorn_d_,
                      dhorn_r_, dhorn_a, dhorn_d_
                );
   input clk;
 
-  `input(command_r,   command_a,   command_a_, [(`DATAWIDTH-1):0], command_d)
+  `input(in_r,     in_a,     in_a_,   [(`DATAWIDTH-1):0],         in_d)
   `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
   `defreg(ihorn_d_,                   [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
-  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
-  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0], dhorn_d)
+  `output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0],      dhorn_d_)
+  `defreg(dhorn_d_,                   [(`PACKET_WIDTH-1):0],      dhorn_d)
 
   reg ihorn_full;
   reg dhorn_full;
@@ -39,17 +39,17 @@ module execute (clk, command_r,   command_a_, command_d,
         dhorn_full = 0;
       end
     end else begin
-      `onread(command_r, command_a)
-        case (command_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
+      `onread(in_r, in_a)
+        case (in_d[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
           0: begin
               ihorn_full  = 1;
-              ihorn_d = command_d;
+              ihorn_d = in_d;
               end
           //01:
           2: begin
               dhorn_full  = 1;
-              `packet_data(dhorn_d) = command_d[23:0];
-              `packet_dest(dhorn_d) = command_d[34:24];
+              `packet_data(dhorn_d) = in_d[23:0];
+              `packet_dest(dhorn_d) = in_d[34:24];
               end
           //11:
         endcase