== FleetSim ==============================================================
+== FPGA ==============================================================
+
+ wire in0_a;
+ wire out0_r;
+ wire [(`DATAWIDTH-1):0] out0_d;
+
+ fifo8 fifo8(clk, rst,
+ in_r, in0_a, in_d,
+ out0_r, out_a, out0_d);
+
+ always @(posedge clk) begin
+ if (!rst) begin
+ `reset
+ end else begin
+ in_a <= in0_a;
+ out_r <= out0_r;
+ out_d <= out0_d;
+ end
+ end
+
== Test =================================================================
// expected output
#expect 9