add dummy test for DRAM

[fleet.git] / ships / Fifo.ship

diff --git a/ships/Fifo.ship b/ships/Fifo.ship
index 663c524..0a620b2 100644 (file)
--- a/ships/Fifo.ship
+++ b/ships/Fifo.ship
@@ -29,6 +29,20 @@ at least 16 words.
 
 == FleetSim ==============================================================
 
+== FPGA ==============================================================
+
+  input  [(`DATAWIDTH-1):0] in_d;
+  output [(`DATAWIDTH-1):0] out_d_;
+  input in_r;
+  output in_a_;
+  output out_r_;
+  input out_a;
+
+  fifo8x37 fifo8x37(clk, rst,
+                    in_r,  in_a_, in_d,
+                    out_r_, out_a, out_d_);
+
+
 == Test =================================================================
 // expected output
 #expect 9
@@ -37,14 +51,21 @@ at least 16 words.
 #ship debug        : Debug
 #ship fifo         : Fifo
 
-debug.in:   [*] take, deliver;
+debug.in:   set ilc=*;  recv, deliver;
 fifo.in:
-  literal 9;
+  set word= 9;
   deliver;
-  [100] take, deliver;
+  set ilc=63;
+  recv, deliver;
+  set ilc=37;
+  recv, deliver;
+
 fifo.out:
-  [99] take, sendto fifo.in;
-  [1]  take, sendto debug.in;
+  set ilc=63;
+  collect, send to fifo.in;
+  set ilc=36;
+  collect, send to fifo.in;
+  collect, send to debug.in;