== FPGA ==============================================================
- wire in_a__;
- wire out_r__;
-
- fifo8x37 fifo8x37(clk, rst,
- in_r, in_a__, in_d,
- out_r__, out_a, out_d_);
-
- always @(posedge clk) begin
- if (!rst) begin
- `reset
- end else begin
- `flush
- out_r <= out_r__;
- in_a <= in_a__;
- end
- end
-
+// not used
== Test =================================================================
// expected output