== FPGA ==============================================================
- wire in0_a;
- wire out0_r;
- wire [(`DATAWIDTH-1):0] out0_d;
-
- fifo8 fifo8(clk, rst,
- in_r, in0_a, in_d,
- out0_r, out_a, out0_d);
-
- always @(posedge clk) begin
- if (!rst) begin
- `reset
- end else begin
- in_a <= in0_a;
- out_r <= out0_r;
- out_d <= out0_d;
- end
- end
+// not used
== Test =================================================================
// expected output
#ship debug : Debug
#ship fifo : Fifo
-debug.in: [*] take, deliver;
+debug.in: set ilc=*; recv, deliver;
fifo.in:
- literal 9;
+ set word= 9;
deliver;
- load repeat counter with 63;
- take, deliver;
- load repeat counter with 37;
- take, deliver;
+ set ilc=63;
+ recv, deliver;
+ set ilc=37;
+ recv, deliver;
fifo.out:
- load repeat counter with 63;
- take, sendto fifo.in;
- load repeat counter with 36;
- take, sendto fifo.in;
- take, sendto debug.in;
+ set ilc=63;
+ collect, send to fifo.in;
+ set ilc=36;
+ collect, send to fifo.in;
+ collect, send to debug.in;