== FPGA ==============================================================
- input [(`DATAWIDTH-1):0] in_d;
- output [(`DATAWIDTH-1):0] out_d_;
- input in_r;
- output in_a_;
- output out_r_;
- input out_a;
-
- fifo8x37 fifo8x37(clk, rst,
- in_r, in_a_, in_d,
- out_r_, out_a, out_d_);
-
+// not used
== Test =================================================================
// expected output