== Ports ===========================================================
data in: in
+
data out: out
== Constants ========================================================
+
== TeX ==============================================================
+
+The {\tt Fifo} ship is a simple fifo. Word-sized delivered to the {\tt
+in} port are enqueued into the fifo, and values which arrive at the
+end of the fifo are provided to the {\tt out} port.
+
+The internal capacity of the fifo is unspecified, but guaranteed to be
+at least 16 words.
+
== Fleeterpreter ====================================================
private Queue<Long> fifo = new LinkedList<Long>();
public void service() {
}
== FleetSim ==============================================================
-== FPGA ==============================================================
-`include "macros.v"
-// fifo *ship*: a 16-deep word-wide fifo
-module fifo (clk,
- in_r, in_a, in_d,
- out_r, out_a, out_d);
-
- input clk;
- input in_r;
- input out_a;
- output in_a;
- output out_r;
- input [(`DATAWIDTH-1):0] in_d;
- output [(`DATAWIDTH-1):0] out_d;
-
- wire [(`DATAWIDTH-1):0] d12;
- wire [(`DATAWIDTH-1):0] d23;
- wire [(`DATAWIDTH-1):0] d34;
-
- fifo4 s1(clk, in_r, in_a, in_d, r12, a12, d12);
- fifo4 s2(clk, r12, a12, d12, r23, a23, d23);
- fifo4 s3(clk, r23, a23, d23, r34, a34, d34);
- fifo4 s4(clk, r34, a34, d34, out_r, out_a, out_d);
+== FPGA ==============================================================
-endmodule
+// not used
== Test =================================================================
// expected output
#ship debug : Debug
#ship fifo : Fifo
-debug.in: [*] take, deliver;
-9: sendto fifo.in;
+debug.in: set ilc=*; recv, deliver;
fifo.in:
- take;
- [100] deliver;
+ set word= 9;
+ deliver;
+ set ilc=63;
+ recv, deliver;
+ set ilc=37;
+ recv, deliver;
+
fifo.out:
- (99) take, sendto fifo.in;
- (1) take, sendto debug.in;
+ set ilc=63;
+ collect, send to fifo.in;
+ set ilc=36;
+ collect, send to fifo.in;
+ collect, send to debug.in;