== FPGA ==============================================================
- input [(`DATAWIDTH-1):0] in_d;
- output [(`DATAWIDTH-1):0] out_d_;
- input in_r;
- output in_a_;
- output out_r_;
- input out_a;
-
- fifo8x37 fifo8x37(clk, rst,
- in_r, in_a_, in_d,
- out_r_, out_a, out_d_);
-
+// not used
== Test =================================================================
// expected output
#ship debug : Debug
#ship fifo : Fifo
-debug.in: [*] take, deliver;
+debug.in: set ilc=*; recv, deliver;
fifo.in:
- literal 9;
+ set word= 9;
deliver;
- load repeat counter with 63;
- take, deliver;
- load repeat counter with 37;
- take, deliver;
+ set ilc=63;
+ recv, deliver;
+ set ilc=37;
+ recv, deliver;
fifo.out:
- load repeat counter with 63;
- take, sendto fifo.in;
- load repeat counter with 36;
- take, sendto fifo.in;
- take, sendto debug.in;
+ set ilc=63;
+ collect, send to fifo.in;
+ set ilc=36;
+ collect, send to fifo.in;
+ collect, send to debug.in;