autogenerate parts of Alu1, Alu2, Lut3 verilog

[fleet.git] / ships / Fifo.ship

diff --git a/ships/Fifo.ship b/ships/Fifo.ship
index f4d8ea1..ff674a4 100644 (file)
--- a/ships/Fifo.ship
+++ b/ships/Fifo.ship
@@ -17,7 +17,7 @@ data  out:  out
         }
     }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 == FPGA ==============================================================
 `include "macros.v"