factor out verilog headers on Alu2 ship

[fleet.git] / ships / Lut.ship

diff --git a/ships/Lut.ship b/ships/Lut.ship
index 91489d7..8e1b90a 100644 (file)
--- a/ships/Lut.ship
+++ b/ships/Lut.ship
@@ -3,15 +3,29 @@ ship: Lut
 == Ports ===========================================================
 data  in:   in1
 data  in:   in2
+data  in:   in3
 data  in:   inLut
 
 data  out:  out
 
 == Constants ========================================================
+
 == TeX ==============================================================
+
+This ship implements a {\bf L}ook {\bf U}p {\bf T}able.  The least
+significant eight bits of the {\tt inLut} value form a truth table
+with two inputs and one output (FIXME: specify the layout).
+
+When values are available at all three inputs they are consumed and a
+value is produced at {\tt out}.  Each bit of {\tt out} is produced by
+looking up the corresponding bits of {\tt in1} and {\tt in2} in the
+{\tt inLut} truth table.
+
 == Fleeterpreter ====================================================
     public void service() {
-        if (box_in1.dataReadyForShip() && box_in2.dataReadyForShip() && box_inLut.dataReadyForShip()) {
+        if (box_in1.dataReadyForShip() &&
+            box_in2.dataReadyForShip() &&
+            box_inLut.dataReadyForShip()) {
             int a      = box_in1.removeDataForShip();
             int b      = box_in2.removeDataForShip();
             int lut    = box_inLut.removeDataForShip();
@@ -24,7 +38,7 @@ data  out:  out
         }
     }
 
-== ArchSim ==============================================================
+== FleetSim ==============================================================
 == FPGA ==============================================================
 // not implemented FIXME