endgenerate
always @(posedge clk) begin
+ if (!rst) begin
+ have_in1 = 0;
+ have_in2 = 0;
+ have_in3 = 0;
+ have_inLut = 0;
+ `reset
+ end else begin
if (!have_in1) begin
`onread(in1_r, in1_a) have_in1 = 1; reg_in1 = in1_d; end
end else
have_inLut = 0;
end
end
+ end
end