eliminate use of the `XXX_draining macro

[fleet.git] / ships / Lut3.ship

diff --git a/ships/Lut3.ship b/ships/Lut3.ship
index e6bd469..4c8401e 100644 (file)
--- a/ships/Lut3.ship
+++ b/ships/Lut3.ship
@@ -62,6 +62,7 @@ is considered ``bit zero'').
 == FleetSim ==============================================================
 == FPGA ==============================================================
 
+  reg          out_draining;
   wire [7:0]              lut;
 
   genvar i;
@@ -76,17 +77,20 @@ is considered ``bit zero'').
   always @(posedge clk) begin
     if (!rst) begin
       `reset
+      out_draining <= 0;
     end else begin
       `flush
       `cleanup
-      if (`out_draining) begin
+      if (out_draining && `out_empty) begin
          `drain_in1
          `drain_in2
          `drain_in3
          `drain_inLut
+         out_draining <= 0;
       end
-      if (`in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+      if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
          `fill_out
+         out_draining <= 1;
       end
     end
   end