== FleetSim ==============================================================
== FPGA ==============================================================
+ reg out_draining;
wire [7:0] lut;
genvar i;
generate
- for(i=0; i<`DATAWIDTH; i=i+1) begin : OUT
+ for(i=0; i<`WORDWIDTH; i=i+1) begin : OUT
assign out_d_[i] = lut[{in3_d[i], in2_d[i], in1_d[i]}];
end
endgenerate
assign lut = inLut_d[7:0];
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
+ out_draining <= 0;
end else begin
- `flush
- if (!in1_r_ && in1_a) in1_a <= 0;
- if (!in2_r_ && in2_a) in2_a <= 0;
- if (!in3_r_ && in3_a) in3_a <= 0;
- if (!inLut_r_ && inLut_a) inLut_a <= 0;
- if (out_r && out_a) begin
- in1_a <= 1;
- in2_a <= 1;
- in3_a <= 1;
- inLut_a <= 1;
- out_r <= 0;
+ `cleanup
+ if (out_draining && `out_empty) begin
+ `drain_in1
+ `drain_in2
+ `drain_in3
+ `drain_inLut
+ out_draining <= 0;
end
- if (in1_r && !in1_a && in2_r && !in2_a && in3_r && !in3_a && inLut_r && !inLut_a && !out_r && !out_a) begin
- out_r <= 1;
+ if (!out_draining && `in1_full && `in2_full && `in3_full && `inLut_full && `out_empty) begin
+ `fill_out
+ out_draining <= 1;
end
end
end
set ilc=*; recv, deliver;
alu.out:
set olc=2;
- [Rq] recv token, collect, send to lut.inLut;
- [Rq] send to alu.in1;
+ head;
+ recv token, collect, send to lut.inLut;
+ send to alu.in1;
tail;
lut.inLut: