assign lut = inLut_d[7:0];
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
out_draining <= 0;
end else begin
alu.out:
set olc=2;
head;
- [Rq] recv token, collect, send to lut.inLut;
- [Rq] send to alu.in1;
+ recv token, collect, send to lut.inLut;
+ send to alu.in1;
tail;
lut.inLut: