adjust ships to use fill/drain/full/empty macros

[fleet.git] / ships / Memory.ship

diff --git a/ships/Memory.ship b/ships/Memory.ship
index 29f0888..cb36dd0 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -193,44 +193,37 @@ sequence guarantee problem mentioned in the previous paragraph.
       dispatching_cbd <= 0;
     end else begin
       `flush
+      `cleanup
       write_flag <= 0;
 
-      if (!inAddrRead_r_  && inAddrRead_a)  inAddrRead_a  <= 0;
-      if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0;
-      if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0;
-      if (!inCBD_r_ &&  inCBD_a)            inCBD_a <= 0;
-
       // assumes we never want a zero-length codebag
-      if ( inCBD_r && !inCBD_a && !out_r && !out_a) begin
+      if (`inCBD_full && `out_empty) begin
         if (!dispatching_cbd) begin
           cursor          <= inCBD_d[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)];
           counter         <= 0;
           dispatching_cbd <= 1;
         end
-        out_r <= 1;
+        `fill_out
         out_w <= 0;
-      end else if (inCBD_r && out_r && out_a) begin
-        out_r <= 0;
+      end else if (`inCBD_full && `out_draining) begin
         if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
           cursor  <= cursor + 1;
           counter <= counter + 1;
         end else begin
-          inCBD_a <= 1;
+          `drain_inCBD
           counter <= 0;
           dispatching_cbd <= 0;
         end
-      end else if (!dispatching_cbd && out_r &&  out_a) begin out_r <= 0;
-      end else if (!dispatching_cbd && !out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
-        inAddrRead_a    <= 1;
-        out_r           <= 1;
-        out_w           <= 0;
-
-      end else if (!dispatching_cbd && !out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
-        // timing note: it's okay to set the *_a flags here because *_d will still
-        // be valid on the *next* cycle, which is all we care about
-        inAddrWrite_a   <= 1;
-        inDataWrite_a   <= 1;
-        out_r           <= 1;
+      end else if (!dispatching_cbd && `out_empty && `inAddrRead_full) begin
+        `drain_inAddrRead
+        `fill_out
+
+      end else if (!dispatching_cbd && `out_empty && `inAddrWrite_full && `inDataWrite_full) begin
+        // timing note: it's okay to drain here because *_d will still
+        // be valid on the *very next* cycle, which is all we care about
+        `drain_inAddrWrite
+        `drain_inDataWrite
+        `fill_out
         write_flag      <= 1;
         out_w           <= 1;
       end