== Ports ===========================================================
data in: inCBD
-data in: inAddr.read
-data in: inAddr.write
-data in: inAddr.readMany
-data in: inAddr.writeMany
-data in: inData
+data in: inAddrRead
+data in: inAddrWrite
+data in: inDataWrite
data in: inStride
data in: inCount
dispatch((int)addr, (int)size);
}
if (count > 0 && writing) {
- if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
- writeMem((int)addr, box_inData.removeDataForShip());
+ if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
+ writeMem((int)addr, box_inDataWrite.removeDataForShip());
box_out.addDataFromShip(0);
count--;
addr += stride;
addr += stride;
}
- } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
- Packet packet = box_inAddr.peekPacketForShip();
+ } else if (box_inAddrRead.dataReadyForShip() && box_out.readyForDataFromShip()) {
+ Packet packet = box_inAddrRead.peekPacketForShip();
if (packet.destination.getDestinationName().equals("read")) {
- box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
- } else if (packet.destination.getDestinationName().equals("write") && box_inData.dataReadyForShip()) {
- writeMem((int)box_inAddr.removeDataForShip(),
- box_inData.removeDataForShip());
+ box_out.addDataFromShip(readMem((int)box_inAddrRead.removeDataForShip()));
+ } else if (packet.destination.getDestinationName().equals("write") && box_inDataWrite.dataReadyForShip()) {
+ writeMem((int)box_inAddrRead.removeDataForShip(),
+ box_inDataWrite.removeDataForShip());
box_out.addDataFromShip(0);
} else if (packet.destination.getDestinationName().equals("writeMany")
&& box_inStride.dataReadyForShip()
&& box_inCount.dataReadyForShip()) {
- addr = box_inAddr.removeDataForShip();
+ addr = box_inAddrRead.removeDataForShip();
stride = box_inStride.removeDataForShip();
count = box_inCount.removeDataForShip();
writing = true;
} else if (packet.destination.getDestinationName().equals("readMany")
&& box_inStride.dataReadyForShip()
&& box_inCount.dataReadyForShip()) {
- addr = box_inAddr.removeDataForShip();
+ addr = box_inAddrRead.removeDataForShip();
stride = box_inStride.removeDataForShip();
count = box_inCount.removeDataForShip();
writing = false;
`define BRAM_ADDR_WIDTH 14
`define BRAM_DATA_WIDTH `INSTRUCTION_WIDTH
`define BRAM_NAME some_bram
-`include "bram.inc"
+
+/* bram.inc */
+module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
+ input clk;
+ input we;
+ input [(`BRAM_ADDR_WIDTH-1):0] a;
+ input [(`BRAM_ADDR_WIDTH-1):0] dpra;
+ input [(`BRAM_DATA_WIDTH-1):0] di;
+ output [(`BRAM_DATA_WIDTH-1):0] spo;
+ output [(`BRAM_DATA_WIDTH-1):0] dpo;
+ reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
+ reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
+ reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
+ always @(posedge clk) begin
+ if (we)
+ ram[a] <= di;
+ read_a <= a;
+ read_dpra <= dpra;
+ end
+ assign spo = ram[read_a];
+ assign dpo = ram[read_dpra];
+endmodule
+/* bram.inc */
module memory (clk,
cbd_r, cbd_a_, cbd_d,
in_addr_r, in_addr_a_, in_addr_d,
+ write_addr_r, write_addr_a_, write_addr_d,
write_data_r, write_data_a_, write_data_d,
stride_r, stride_a_, stride_d,
count_r, count_a_, count_d,
input clk;
`input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
+ `input(write_addr_r, write_addr_a, write_addr_a_, [(2+`DATAWIDTH-1):0], write_addr_d)
`input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
`input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
`input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
`input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
`input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
- `output(ihorn_r, ihorn_r_, ihorn_a, [(`INSTRUCTION_WIDTH-1):0], ihorn_d_)
- `defreg(ihorn_d_, [(`INSTRUCTION_WIDTH-1):0], ihorn_d)
+ `output(ihorn_r, ihorn_r_, ihorn_a, [(`PACKET_WIDTH-1):0], ihorn_d_)
+ `defreg(ihorn_d_, [(`PACKET_WIDTH-1):0], ihorn_d)
`output(dhorn_r, dhorn_r_, dhorn_a, [(`PACKET_WIDTH-1):0], dhorn_d_)
`defreg(dhorn_d_, [(`PACKET_WIDTH-1):0], dhorn_d)
if (!in_addr_r && in_addr_a) in_addr_a = 0;
if (!write_data_r && write_data_a) write_data_a = 0;
+ if (!write_addr_r && write_addr_a) write_addr_a = 0;
if (command_valid_read) begin
command_valid_read <= 0;
send_read <= 0;
end
- end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
+ end else if (in_addr_r) begin
in_addr_a = 1;
send_read <= 1;
current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
- end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
- in_addr_a = 1;
+ end else if (write_addr_r && write_data_r) begin
+ write_addr_a = 1;
write_data_a = 1;
send_done <= 1;
write_flag <= 1;
- in_addr <= in_addr_d[(`DATAWIDTH-1):0];
+ in_addr <= write_addr_d[(`DATAWIDTH-1):0];
write_data <= write_data_d;
end else if (ihorn_full && launched) begin
case (command[(`INSTRUCTION_WIDTH-1):(`INSTRUCTION_WIDTH-2)])
0: begin
ihorn_full <= 1;
- ihorn_d <= command;
+ `packet_data(ihorn_d) <= `instruction_data(command);
+ `packet_dest(ihorn_d) <= `instruction_dest(command);
end
1: begin
dhorn_full <= 1;
+== Test ==============================================================
+// expected output
+#expect 12
+#expect 13
+#expect 14
+
+// ships required in order to run this code
+#ship debug : Debug
+#ship memory : Memory
+
+// instructions not in any codebag are part of the "root codebag"
+// which is dispatched when the code is loaded
+
+BOB: sendto memory.inCBD;
+memory.inCBD: [*] take, deliver;
+debug.in: [*] take, deliver;
+
+
+// This codebag illustrates how to do a loop. Notice that this
+// is actually an uncontrolled data emitter -- it could clog the
+// switch fabric!
+
+BOB: {
+ 12: sendto debug.in;
+ 13: sendto debug.in;
+ 14: sendto debug.in;
+}
== Constants ========================================================
== TeX ==============================================================
+\begin{verbatim}
+TODO: count/stride
+TODO: multiple interfaces to a single memory
+\end{verbatim}
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>