== FPGA ==============================================================
+ reg write_flag;
+ reg [(`BRAM_ADDR_WIDTH-1):0] cursor;
+ wire [(`BRAM_ADDR_WIDTH-1):0] addr1;
+
+ // bram //////////////////////////////////////////////////////////////////////////////
+`define BRAM_ADDR_WIDTH 14
+`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))
+
+ reg [(`WORDWIDTH-1):0] ram [((`BRAM_SIZE)-1):0];
+ reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
+ reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
+ always @(posedge clk) begin
+ if (write_flag)
+ ram[addr1] <= inDataWrite_d;
+ read_a <= addr1;
+ read_dpra <= cursor;
+ end
+
+ ////////////////////////////////////////////////////////////////////////////////
+
wire [(`WORDWIDTH-1):0] out1;
wire [(`WORDWIDTH-1):0] out2;
+ assign out1 = ram[read_a];
+ assign out2 = ram[read_dpra];
+
reg [(`CODEBAG_SIZE_BITS-1):0] counter;
- reg [(`BRAM_ADDR_WIDTH-1):0] cursor;
initial cursor = 0;
initial counter = 0;
- reg write_flag;
reg out_w;
reg dispatching_cbd;
initial write_flag = 0;
initial dispatching_cbd = 0;
- wire [(`BRAM_ADDR_WIDTH-1):0] addr1;
assign addr1 = write_flag ? inAddrWrite_d[(`WORDWIDTH-1):0] : inAddrRead_d[(`WORDWIDTH-1):0];
- bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
assign out_d_ = { out_w , (dispatching_cbd ? out2 : out1) };
end
`fill_out
out_w <= 0;
+
end else if (`inCBD_full && `out_draining) begin
if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
cursor <= cursor + 1;
counter <= 0;
dispatching_cbd <= 0;
end
+
end else if (!dispatching_cbd && `out_empty && `inAddrRead_full) begin
`drain_inAddrRead
`fill_out
+ out_w <= 0;
end else if (!dispatching_cbd && `out_empty && `inAddrWrite_full && `inDataWrite_full) begin
// timing note: it's okay to drain here because *_d will still