data in: inAddrRead
data in: inAddrWrite
data in: inDataWrite
-data in: inStride
-data in: inCount
data out: out
-data out: outIhorn
== TeX ==============================================================
The {\tt Memory} ship represents an interface to a storage space,
which can be used to read from it or write to it. This storage space
-might be a fast on-chip cache, off chip DRAM, or perhaps even a disk drive.
+might be a fast on-chip cache, off chip DRAM, or perhaps even a disk
+drive.
+
+Generally, distinct {\tt Memory} ships do not access the same backing
+storage, although this is not strictly prohibited.
+
+Each {\tt Memory} ship may have multiple {\it interfaces}, numbered
+starting with {\tt 0}. Each interface may have any subset of the
+following docks: {\tt inCBD}, {\tt inAddrRead}, {\tt inAddrWrite},
+{\tt inDataWrite}, and {\tt out}. If {\tt inCBD} or {\tt inAddrRead}
+is present on an interface, then {\tt out} must be present as well.
+If {\tt inAddrWrite} is present then {\tt inDataWrite} must be present
+as well.
+
+Each interface serializes the operations presented to it; this means
+that an interface with both read and write capabilities will not be
+able to read and write concurrently. Instead, a {\tt Memory} ship
+with the ability to read and write concurrently should have two
+interfaces, one which is read-only and one which is write-only.
There may be multiple {\tt Memory} ships which interface to the same
physical storage space. An implementation of Fleet must provide
\subsection*{Reading}
When a word is delivered to {\tt inAddrRead}, the word residing in
-memory at that address is provided at {\tt out}.
+memory at that address is provided at {\tt out}. The {\tt c-flag} at
+the {\tt out} port is set to zero.
\subsection*{Writing}
the word at {\tt inDataWrite} is written to the address specified by
{\tt inAddrWrite}. Once the word is successfully committed to memory,
the value {\tt inAddr+inStride} is provided at {\tt out} (that is, the
-address of the next word to be written).
+address of the next word to be written). The {\tt c-flag} at
+the {\tt out} port is set to one.
\subsection*{To Do}
private long addr = 0;
private boolean writing = false;
+ private Queue<Long> toDispatch = new LinkedList<Long>();
public void service() {
-/*
- if (box_inCBD.dataReadyForShip()) {
+
+ if (toDispatch.size() > 0) {
+ //if (!box_out.readyForDataFromShip()) return;
+ //box_out.addDataFromShip(toDispatch.remove());
+ getInterpreter().dispatch(getInterpreter().readInstruction(toDispatch.remove(), getDock("out")));
+ }
+
+ if (box_inCBD.dataReadyForShip() && box_out.readyForDataFromShip()) {
long val = box_inCBD.removeDataForShip();
long addr = val >> 6;
long size = val & 0x3f;
- dispatch((int)addr, (int)size);
+ for(int i=0; i<size; i++)
+ toDispatch.add(readMem((int)(addr+i)));
}
-*/
if (count > 0) {
if (writing) {
if (box_inDataWrite.dataReadyForShip() && box_out.readyForDataFromShip()) {
writing = false;
} else if (box_inAddrWrite.dataReadyForShip()) {
-// addr = box_inAddrWrite.peekPacketForShip().value;
- box_inAddrWrite.removeDataForShip();
+ addr = box_inAddrWrite.removeDataForShip();
stride = 0;
count = 1;
writing = true;
== FPGA ==============================================================
- reg [(`CODEBAG_SIZE_BITS-1):0] cursor;
- reg write_flag;
+ wire [(`DATAWIDTH-1):0] out1;
+ wire [(`DATAWIDTH-1):0] out2;
+
+ reg [(`CODEBAG_SIZE_BITS-1):0] counter;
+ reg [(`BRAM_ADDR_WIDTH-1):0] cursor;
+ initial cursor = 0;
+ initial counter = 0;
+
+ reg write_flag;
+ reg dispatching_cbd;
+ initial write_flag = 0;
+ initial dispatching_cbd = 0;
wire [(`BRAM_ADDR_WIDTH-1):0] addr1;
- wire [(`BRAM_ADDR_WIDTH-1):0] addr2;
- wire [(`BRAM_DATA_WIDTH-1):0] val2;
assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
- assign addr2 = (inCBD_d[(`INSTRUCTION_WIDTH-1):(`CODEBAG_SIZE_BITS)])+cursor;
+ bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
- bram14 mybram(clk, rst, write_flag, addr1, addr2, inDataWrite_d, out_d_, val2);
+ assign out_d_ = dispatching_cbd ? out2 : out1;
always @(posedge clk) begin
if (!rst) begin
`reset
- cursor <= 0;
+ cursor <= 0;
+ counter <= 0;
+ write_flag <= 0;
+ dispatching_cbd <= 0;
end else begin
+ `flush
write_flag <= 0;
- if (!inAddrRead_r && inAddrRead_a) inAddrRead_a <= 0;
- if (!inDataWrite_r && inDataWrite_a) inDataWrite_a <= 0;
- if (!inAddrWrite_r && inAddrWrite_a) inAddrWrite_a <= 0;
-
- if ( out_r && !out_a) begin
- end else if ( out_r && out_a) begin out_r <= 0;
- end else if (!out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
+ if (!inAddrRead_r_ && inAddrRead_a) inAddrRead_a <= 0;
+ if (!inDataWrite_r_ && inDataWrite_a) inDataWrite_a <= 0;
+ if (!inAddrWrite_r_ && inAddrWrite_a) inAddrWrite_a <= 0;
+ if (!inCBD_r_ && inCBD_a) inCBD_a <= 0;
+
+ // assumes we never want a zero-length codebag
+ if ( inCBD_r && !inCBD_a && !out_r && !out_a) begin
+ if (!dispatching_cbd) begin
+ cursor <= inCBD_d[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)];
+ counter <= 0;
+ dispatching_cbd <= 1;
+ end
+ out_r <= 1;
+ end else if (inCBD_r && out_r && out_a) begin
+ out_r <= 0;
+ if (counter != inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
+ cursor <= cursor + 1;
+ counter <= counter + 1;
+ end else begin
+ inCBD_a <= 1;
+ counter <= 0;
+ dispatching_cbd <= 0;
+ end
+ end else if (!dispatching_cbd && out_r && out_a) begin out_r <= 0;
+ end else if (!dispatching_cbd && !out_r && !out_a && inAddrRead_r && !inAddrRead_a) begin
inAddrRead_a <= 1;
out_r <= 1;
- end else if (!out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
+ end else if (!dispatching_cbd && !out_r && !out_a && inAddrWrite_r && inDataWrite_r) begin
// timing note: it's okay to set the *_a flags here because *_d will still
// be valid on the *next* cycle, which is all we care about
inAddrWrite_a <= 1;
inDataWrite_a <= 1;
out_r <= 1;
write_flag <= 1;
-
- end else if ( outIhorn_r && outIhorn_a) begin outIhorn_r <= 0;
- end else if (!inCBD_r && inCBD_a) begin inCBD_a <= 0;
- end else if ( inCBD_r && !inCBD_a && !outIhorn_r && !outIhorn_a) begin
- if (cursor < inCBD_d[(`CODEBAG_SIZE_BITS-1):0]) begin
- outIhorn_d <= val2;
- outIhorn_r <= 1;
- cursor <= cursor + 1;
- end else begin
- inCBD_a <= 1;
- cursor <= 0;
- end
end
end
end
== Test ==============================================================
+// FIXME: test c-flag at out dock
+// FIXME: rename to inCBD0, inAddrWrite0, etc
+
// expected output
#expect 12
#expect 13
// instructions not in any codebag are part of the "root codebag"
// which is dispatched when the code is loaded
+memory.out:
+ set ilc=*; collect packet, send;
+
memory.inCBD:
- literal BOB;
+ set word= BOB;
deliver;
BOB: {
debug.in:
- literal 12; deliver;
- literal 13; deliver;
- literal 14; deliver;
+ set word= 12; deliver;
+ set word= 13; deliver;
+ set word= 14; deliver;
}
projects / fleet.git / blobdiff