replace DATAWIDTH with WORDWIDTH

[fleet.git] / ships / Memory.ship

diff --git a/ships/Memory.ship b/ships/Memory.ship
index cb36dd0..7245737 100644 (file)
--- a/ships/Memory.ship
+++ b/ships/Memory.ship
@@ -161,8 +161,8 @@ sequence guarantee problem mentioned in the previous paragraph.
 
 == FPGA ==============================================================
 
-  wire [(`DATAWIDTH-1):0] out1;
-  wire [(`DATAWIDTH-1):0] out2;
+  wire [(`WORDWIDTH-1):0] out1;
+  wire [(`WORDWIDTH-1):0] out2;
 
   reg [(`CODEBAG_SIZE_BITS-1):0]   counter;
   reg [(`BRAM_ADDR_WIDTH-1):0]     cursor;
@@ -176,7 +176,7 @@ sequence guarantee problem mentioned in the previous paragraph.
   initial dispatching_cbd = 0;
 
   wire [(`BRAM_ADDR_WIDTH-1):0]   addr1;
-  assign addr1 = write_flag ? inAddrWrite_d[(`DATAWIDTH-1):0] : inAddrRead_d[(`DATAWIDTH-1):0];
+  assign addr1 = write_flag ? inAddrWrite_d[(`WORDWIDTH-1):0] : inAddrRead_d[(`WORDWIDTH-1):0];
   bram14 mybram(clk, rst, write_flag, addr1, cursor, inDataWrite_d, out1, out2);
 
   assign out_d_ = { out_w , (dispatching_cbd ? out2 : out1) };
@@ -199,7 +199,7 @@ sequence guarantee problem mentioned in the previous paragraph.
       // assumes we never want a zero-length codebag
       if (`inCBD_full && `out_empty) begin
         if (!dispatching_cbd) begin
-          cursor          <= inCBD_d[(`DATAWIDTH-1):(`CODEBAG_SIZE_BITS)];
+          cursor          <= inCBD_d[(`WORDWIDTH-1):(`CODEBAG_SIZE_BITS)];
           counter         <= 0;
           dispatching_cbd <= 1;
         end