dispatch(base, size);
}
+ private long stride = 0;
+ private long count = 0;
+ private long addr = 0;
+ private boolean writing = false;
+
public void service() {
if (box_inCBD.dataReadyForShip()) {
long val = box_inCBD.removeDataForShip();
long size = val & 0x3f;
dispatch((int)addr, (int)size);
}
- if (box_inAddr.dataReadyForShip() && box_out.readyForItemFromShip()) {
+ if (count > 0 && writing) {
+ if (box_inData.dataReadyForShip() && box_out.readyForDataFromShip()) {
+ writeMem((int)addr, box_inData.removeDataForShip());
+ box_out.addDataFromShip(0);
+ count--;
+ addr += stride;
+ }
+
+ } else if (count > 0 && !writing) {
+ if (box_out.readyForDataFromShip()) {
+ box_out.addDataFromShip(readMem((int)addr));
+ count--;
+ addr += stride;
+ }
+
+ } else if (box_inAddr.dataReadyForShip() && box_out.readyForDataFromShip()) {
Packet packet = box_inAddr.peekPacketForShip();
if (packet.destination.getDestinationName().equals("read")) {
box_out.addDataFromShip(readMem((int)box_inAddr.removeDataForShip()));
writeMem((int)box_inAddr.removeDataForShip(),
box_inData.removeDataForShip());
box_out.addDataFromShip(0);
+ } else if (packet.destination.getDestinationName().equals("writeMany")
+ && box_inStride.dataReadyForShip()
+ && box_inCount.dataReadyForShip()) {
+ addr = box_inAddr.removeDataForShip();
+ stride = box_inStride.removeDataForShip();
+ count = box_inCount.removeDataForShip();
+ writing = true;
+ } else if (packet.destination.getDestinationName().equals("readMany")
+ && box_inStride.dataReadyForShip()
+ && box_inCount.dataReadyForShip()) {
+ addr = box_inAddr.removeDataForShip();
+ stride = box_inStride.removeDataForShip();
+ count = box_inCount.removeDataForShip();
+ writing = false;
}
}
}
);
input clk;
- `input(in_addr_r, in_addr_a, in_addr_a_, [(`DATAWIDTH-1):0], in_addr_d)
+ `input(in_addr_r, in_addr_a, in_addr_a_, [(2+`DATAWIDTH-1):0], in_addr_d)
`input(write_data_r, write_data_a, write_data_a_, [(`DATAWIDTH-1):0], write_data_d)
`input(stride_r, stride_a, stride_a_, [(`DATAWIDTH-1):0], stride_d)
`input(count_r, count_a, count_a_, [(`DATAWIDTH-1):0], count_d)
- `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
- `defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
+ `output(out_r, out_r_, out_a, [(`DATAWIDTH-1):0], out_d_)
+ //`defreg(out_d_, [(`DATAWIDTH-1):0], out_d)
`input(preload_r, preload_a, preload_a_, [(`DATAWIDTH-1):0], preload_d)
`input(cbd_r, cbd_a, cbd_a_, [(`DATAWIDTH-1):0], cbd_d)
reg [(`INSTRUCTION_WIDTH-1):0] command;
reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
reg send_done;
+ reg send_read;
reg [(`INSTRUCTION_WIDTH-(2+`DESTINATION_ADDRESS_BITS)):0] temp;
reg [(`DATAWIDTH-1):0] data;
initial launched = 0;
some_bram mybram(clk, write_flag, in_addr, current_instruction_read_from, write_data, not_connected, ramread);
+ assign out_d_ = ramread;
always @(posedge clk) begin
send_done <= 0;
end
- end else if (in_addr_r && write_data_r) begin
- in_addr_a = 1;
+ end else if (send_read) begin
+ `onwrite(out_r, out_a)
+ send_read <= 0;
+ end
+
+ end else if (in_addr_r && !in_addr_d[`DATAWIDTH]) begin
+ in_addr_a = 1;
+ send_read <= 1;
+ current_instruction_read_from <= in_addr_d[(`DATAWIDTH-1):0];
+
+ end else if (in_addr_r && in_addr_d[`DATAWIDTH] && write_data_r) begin
+ in_addr_a = 1;
write_data_a = 1;
send_done <= 1;
write_flag <= 1;
- in_addr <= in_addr_d;
+ in_addr <= in_addr_d[(`DATAWIDTH-1):0];
write_data <= write_data_d;
end else if (ihorn_full && launched) begin
== Constants ========================================================
== TeX ==============================================================
+\begin{verbatim}
+TODO: count/stride
+TODO: multiple interfaces to a single memory
+\end{verbatim}
== Contributors =========================================================
Adam Megacz <megacz@cs.berkeley.edu>