== FPGA ==============================================================
- reg [(`DATAWIDTH):0] out_d;
+ reg [(`WORDWIDTH):0] out_d;
assign out_d_ = out_d;
reg full;
shamt <= 0;
full <= 1;
end else if (!shamt_eq) begin
- out_d <= { out_d[0], out_d[0], out_d[`DATAWIDTH-1:1] };
+ out_d <= { out_d[0], out_d[0], out_d[`WORDWIDTH-1:1] };
shamt <= shamt+1;
end else begin
`drain_in