long data = box_in.removeDataForShip();
long mask = ~((-1L) << getInterpreter().getWordWidth());
data = data & mask;
- box_out.addDataFromShip(((data << amount) | (data >> (getInterpreter().getWordWidth()-amount))) & mask);
+ long res = ((data >> amount) | (data << (getInterpreter().getWordWidth()-amount))) & mask;
+ box_out.addDataFromShip(res, (res & (1L << (getInterpreter().getWordWidth()-1)))!=0);
}
}
== FPGA ==============================================================
- reg [(`DATAWIDTH):0] out_d;
+ reg [(`WORDWIDTH):0] out_d;
assign out_d_ = out_d;
+ reg full;
+ initial full = 0;
+
reg [5:0] shamt;
initial shamt = 0;
assign shamt_eq = (shamt[5:0] == (inAmount_d[5:0]));
always @(posedge clk) begin
- if (!rst) begin
+ if (rst) begin
`reset
+ full <= 0;
end else begin
- `flush
- if (!in_r_ && in_a && !inAmount_r) in_a <= 0;
- if (!inAmount_r_ && inAmount_a) inAmount_a <= 0;
- if (out_r && out_a) out_r <= 0;
- if (in_r && !in_a && inAmount_r && !inAmount_a && !out_r && !out_a) begin
- in_a <= 1;
- out_d <= { 1'b0, in_d };
- shamt <= 0;
- end else if (in_a && inAmount_r && !inAmount_a && !out_r && !out_a) begin
- if (!shamt_eq) begin
- out_d <= { out_d[0], out_d[0], out_d[`DATAWIDTH-1:1] };
- shamt <= shamt+1;
+ `cleanup
+ if (`in_full && `inAmount_full && `out_empty) begin
+ if (!full) begin
+ out_d <= { 1'b0, in_d };
+ shamt <= 0;
+ full <= 1;
+ end else if (!shamt_eq) begin
+ out_d <= { out_d[0], out_d[0], out_d[`WORDWIDTH-1:1] };
+ shamt <= shamt+1;
end else begin
- inAmount_a <= 1;
- out_r <= 1;
+ `drain_in
+ `drain_inAmount
+ `fill_out
+ full <= 0;
end
end
end
deliver;
rotator.out:
set olc=3;
- [Rq] collect, send to debug.in;
- [Rq] set flags a=c, b=b;
- [Rq] [!a] set word=0;
- [Rq] [a] set word=1;
- [Rq] send to debug.in;
+ head;
+ collect, send to debug.in;
+ set flags a=c, b=b;
+ [!a] set word=0;
+ [a] set word=1;
+ send to debug.in;
tail;