data in: inY
data in: inData
+percolate up: vga_psave 1
+percolate up: vga_hsync 1
+percolate up: vga_vsync 1
+percolate up: vga_sync 1
+percolate up: vga_blank 1
+percolate up: vga_r 8
+percolate up: vga_g 8
+percolate up: vga_b 8
+percolate up: vga_clkout 1
+
== TeX ==============================================================
== Fleeterpreter ====================================================
== FPGA ==============================================================
+ wire vga_clk_unbuffered; // synthesis attribute period of vga_clk_unbuffered is "40 ns";
+
+ wire vga_clk;
+ wire vga_clk_fb;
+
+ BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
+ DCM // 25Mhz VGA clock
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(16),
+ .CLKIN_PERIOD("20 ns")
+ ) vgadcm (
+ .CLKIN (clk),
+ .CLKFB(vga_clk_fb),
+ .CLKFX (vga_clk_unbuffered),
+ .CLK0 (vga_clk_fb)
+ );
+
wire [31:0] vga_pixel_addr_;
wire vga_pixel_r;