import com.sun.async.test.JtagTester;
import com.sun.async.test.ManualPowerChannel;
import com.sun.async.test.NanosimModel;
+import com.sun.async.test.NanosimLogicSettable;
import com.sun.async.test.HsimModel;
import com.sun.async.test.VerilogModel;
import com.sun.async.test.Netscan4;
import edu.berkeley.fleet.api.Instruction.Set.SetSource;
import edu.berkeley.fleet.marina.MarinaFleet;
import edu.berkeley.fleet.marina.MarinaPath;
+import com.sun.async.test.*;
/**
* Tests for Marina
fatal(true, "unrecognized CmdArgs.Mode");
return;
}
+
model = cmdArgs.useVerilog
? new VerilogModel()
: cmdArgs.useHsim
? new HsimModel()
+ : cmdArgs.silicon
+ ? new SiliconChip()
: new NanosimModel();
- ((SimulationModel)model).setOptimizedDirectReadsWrites(true);
+ if (model instanceof SimulationModel)
+ ((SimulationModel)model).setOptimizedDirectReadsWrites(true);
CYCLE_TIME_NS = cmdArgs.useVerilog ? (100*20) : 0.250;
- int khz = model instanceof VerilogModel ? 100000 : cmdArgs.jtagShift ? 20000 : 1000000;
-
- prln("constructing jtag controller");
- JtagTester tester = ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO");
- tester.printInfo = false;
+ int khz =
+ model instanceof VerilogModel
+ ? 100000
+ : cmdArgs.jtagShift
+ ? 20000
+ : model instanceof ChipModel
+ ? 1
+ : 1000000;
+
+ System.err.println("constructing jtag controller");
+ JtagTester tester =
+ model instanceof SimulationModel
+ ? ((SimulationModel)model).createJtagTester("TCK", "TMS", "TRSTb", "TDI", "TDO")
+ : new Netscan4("jtag3", 2);
+ Logger.setLogInits(true);
+ tester.setLogSets(true);
+ tester.setLogOthers(true);
+ tester.setAllLogging(true);
+ tester.printInfo = true;
ChainControls ccs = new ChainControls();
PowerChannel pc = new ManualPowerChannel("pc", false);
marina = new Marina(ccs, model, !cmdArgs.jtagShift, indenter);
+ if (model instanceof NanosimModel) {
+ NanosimLogicSettable mc = (NanosimLogicSettable)
+ ((SimulationModel)model).createLogicSettable(Marina.MASTER_CLEAR);
+ mc.setInitState(true);
+ }
+
+ prln("starting model");
if (model instanceof VerilogModel)
((SimulationModel)model).start("verilog", "marina.v", VerilogModel.DUMPVARS, !cmdArgs.jtagShift);
else if (model instanceof HsimModel)
((SimulationModel)model).start("hsim64", netListName, 0, !cmdArgs.jtagShift);
- else
+ else if (model instanceof NanosimModel)
((SimulationModel)model).start("nanosim -c cfg", netListName, 0, !cmdArgs.jtagShift);
+ else
+ {}
+ prln("model started");
- /*
- ccC.resetInBits();
- ccC.shift(Marina.CONTROL_CHAIN, false, true);
- */
+ model.waitNS(1000);
+ prln("deasserting master clear");
+ if (model instanceof SimulationModel)
+ ((SimulationModel)model).setNodeState(Marina.MASTER_CLEAR, 0);
+ else
+ prln("FIXME: need to deassert master clear");
+ model.waitNS(1000);
- cc.resetInBits();
- cc.shift(Marina.CONTROL_CHAIN, false, true);
+ if (cmdArgs.testNum!=0 && cmdArgs.testNum!=1) {
+ cc.resetInBits();
+ cc.shift(Marina.CONTROL_CHAIN, false, true);
+ }
doOneTest(cmdArgs.testNum);
-
- ((SimulationModel)model).finish();
+
+ if (model instanceof SimulationModel)
+ ((SimulationModel)model).finish();
}
private void doSilicon() {
model = new SiliconChip();