support for both slow and fast fifos

[fleet.git] / src / edu / berkeley / fleet / fpga / FifoModule.java

diff --git a/src/edu/berkeley/fleet/fpga/FifoModule.java b/src/edu/berkeley/fleet/fpga/FifoModule.java
index 0741e0c..21ceab6 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/FifoModule.java
+++ b/src/edu/berkeley/fleet/fpga/FifoModule.java
@@ -15,16 +15,20 @@ import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
 public class FifoModule extends Module {
     private int len;
     private int width;
-    public FifoModule(int len, int width) {
-        super("fifo"+len+"x"+width);
+    private boolean doubleSpeed;
+    public FifoModule(int len, int width) { this(len, width, false); }
+    public FifoModule(int len, int width, boolean doubleSpeed) {
+        super("fifo"+len+"x"+width+(doubleSpeed?"_2x":""));
         this.len = len;
         this.width = width;
+        this.doubleSpeed = doubleSpeed;
         Module.SourcePort  in  = createInputPort("in", width);
         Module.SinkPort    out = createOutputPort("out", width);
         Module.InstantiatedModule[] stages = new Module.InstantiatedModule[len];
         if (len==0) {
             in.connect(out);
         } else if (len==1) {
+            if (doubleSpeed) throw new RuntimeException();
             new Event(new Object[] { in, out },
                       new Action[] { in, out, new AssignAction(out, in) });
         } else {
@@ -53,10 +57,16 @@ public class FifoModule extends Module {
             pw.println("`define ADDR_BITS "+dislog(len));
             pw.println("`define WIDTH " + width);
             pw.println("`define MODULE_NAME "+name);
+            if (doubleSpeed) {
+                pw.println("`define DELAY 2");
+            } else {
+                pw.println("`define DELAY 5");
+            }
             pw.println("`include \"ramfifo.inc\"");
             pw.flush();
             return;
         }
+        if (doubleSpeed) throw new RuntimeException();
 
         super.dump(prefix);
         return;