import edu.berkeley.fleet.two.*;
import static edu.berkeley.fleet.two.FleetTwoFleet.*;
import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
+import static edu.berkeley.fleet.fpga.verilog.Verilog.PercolatedPort;
-/*
-=> get rid of getInputPort(String) and instead use members
-=> clean up fabricelement methods
-=> get rid of addcrap
-=> automatic width-setting on ports
-=> nuke DATAWIDTH?
- => serdes and fastclock/slowclock?
-*/
-
public class Fpga extends FleetTwoFleet {
public Module top;
pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
pw.println("`define BRAM_ADDR_WIDTH 14");
- pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
+ pw.println("`define BRAM_DATA_WIDTH `WORDWIDTH");
pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
pw.println("`define BRAM_NAME bram14");
pw.println("`include \"bram.inc\"");
this.top = top;
debugShip = createShip("Debug", "debug");
- boolean small = false;
+ //boolean small = false;
+ boolean small = true;
createShip("Memory", "memory1");
if (small) {
- createShip("Fifo", "fifo");
- createShip("Alu", "alu");
+ for(int i=0; i<2; i++)
+ createShip("Fifo", "fifo"+i);
+ for(int i=0; i<2; i++)
+ createShip("Alu", "alu"+i);
createShip("Counter", "counter");
createShip("CarrySaveAdder", "csa1");
createShip("Rotator", "rotator");
for(int i=0; i<3; i++)
createShip("Alu", "alu"+i);
- /*
- for(int i=0; i<2; i++)
+ for(int i=0; i<1; i++)
createShip("Fifo", "fifo"+i);
- */
for(int i=0; i<14; i++)
createShip("Counter", "counter"+i);
numdocks++;
}
}
- //System.err.println("dock count = " + numdocks);
ArrayList dests = new ArrayList<FabricElement>();
ArrayList sources = new ArrayList<FabricElement>();
sources.addAll(inbox_sources);
FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
((FunnelModule.FunnelInstance)source).out = top_funnel;
- //top_horn.addInput(top_funnel, top_funnel.getOutputPort());
top_funnel.addOutput(top_horn, top_horn.getInputPort());
-
- //Module.SourcePort debug_in = top.createWireSourcePort("debug_in", WIDTH_PACKET);
Module.SinkPort debug_in = top_funnel.getInputPort("in1");
top.new Event(new Object[] { in, "count<=7" },
new Object[] { new SimpleAction(temp_in.getVerilogName()+" <= {" + temp_in.getVerilogName() + "["+(WIDTH_PACKET-(1+8))+":0], in[7:0] };"),
- new SimpleAction("count <= count+1;"),
+ new AssignAction(count, count.getVerilogName()+"+1"),
in
});
top.new Event(new Object[] { debug_in, "count>7" },
- new Object[] { new SimpleAction(" count <= 0; "),
+ new Object[] { new AssignAction(count, "0"),
new AssignAction(debug_in, temp_in),
debug_in
});
top.new Event(new Object[] { out, debug_out },
new Object[] { new SimpleAction(out.getVerilogName()+" <= ("+debug_out.getVerilogName()+">> (count_out*8));"),
- new SimpleAction("if (count_out >= 5) begin "+
- "count_out <= 0; "+debug_out.getVerilogName()+"_a <= 1; end"+
- " else count_out <= count_out+1; "),
+ new ConditionalAction("count_out >= 5", debug_out),
+ new ConditionalAction("count_out >= 5", new AssignAction(count_out, "0")),
+ new ConditionalAction("count_out < 5", new AssignAction(count_out, "count_out+1")),
out });
}
boolean debug = "debug".equals(filename);
- pw.println("`define DATAWIDTH "+WIDTH_WORD);
+ pw.println("`define WORDWIDTH "+WIDTH_WORD);
pw.println("`define CODEBAG_SIZE_BITS "+CBD_SIZE.valmaskwidth);
pw.println();
pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
if (dd.isInputDock()) {
- pw.println("`define drain_"+name+" "+name+"_a <= 1");
+ pw.println("`define drain_"+name+" "+name+"_a <= 1;");
} else {
- pw.println("`define fill_"+name+" "+name+"_r <= 1");
+ pw.println("`define fill_"+name+" "+name+"_r <= 1;");
+ pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
}
}
+ if (debug) {
+ String name = "out";
+ pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
+ pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
+ pw.println("`define fill_"+name+" "+name+"_r <= 1;");
+ pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
+ }
pw.print("`define reset ");
for(DockDescription bb : sd) {
if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
else pw.print(bb_name+"_r <= 0; ");
}
+ if (debug) {
+ String bb_name = "out";
+ pw.print(bb_name+"_r <= 0; ");
+ }
+ pw.println();
+
+ pw.print("`define cleanup ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
+ else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
+ }
+ if (debug) {
+ String bb_name = "out";
+ pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
+ }
pw.println();
+ // FIXME: this corresponds to something
+ /*
+ pw.print("`define flush_happening (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]");
+ pw.println(")");
+ */
+
pw.print("`define flush ");
for(DockDescription bb : sd)
if (bb.isInputDock())
pw.println(" , out_a");
pw.println(" , out_d_");
}
- if (filename.equals("dram")) {
- pw.println(" , dram_addr_");
- pw.println(" , dram_addr_r_");
- pw.println(" , dram_addr_a");
- pw.println(" , dram_isread_");
- pw.println(" , dram_write_data_");
- pw.println(" , dram_write_data_push_");
- pw.println(" , dram_write_data_full");
- pw.println(" , dram_read_data");
- pw.println(" , dram_read_data_pop_");
- pw.println(" , dram_read_data_empty");
- pw.println(" , dram_read_data_latency");
- }
- if (filename.equals("ddr2")) {
- pw.println(" , ddr2_addr_");
- pw.println(" , ddr2_addr_r_");
- pw.println(" , ddr2_addr_a");
- pw.println(" , ddr2_isread_");
- pw.println(" , ddr2_write_data_");
- pw.println(" , ddr2_write_data_push_");
- pw.println(" , ddr2_write_data_full");
- pw.println(" , ddr2_read_data");
- pw.println(" , ddr2_read_data_pop_");
- pw.println(" , ddr2_read_data_empty");
- pw.println(" , ddr2_read_data_latency");
- }
- if (filename.equals("video")) {
- pw.println(" , vga_clk");
- pw.println(" , vga_psave");
- pw.println(" , vga_hsync");
- pw.println(" , vga_vsync");
- pw.println(" , vga_sync");
- pw.println(" , vga_blank");
- pw.println(" , vga_r");
- pw.println(" , vga_g");
- pw.println(" , vga_b");
- pw.println(" , vga_clkout");
+ for(PercolatedPort pp : sd.percolatedPorts) {
+ pw.print(" , ");
+ pw.println(pp.name);
}
pw.println(" );");
pw.println();
pw.println(" input clk;");
pw.println(" input rst;");
- if (filename.equals("debug")) {
- pw.println(" output ["+WIDTH_WORD+":0] out_d_;");
- pw.println(" input out_a;");
- pw.println(" output out_r_;");
- }
- if (filename.equals("dram")) {
- pw.println("output [31:0] dram_addr_;");
- pw.println("output dram_addr_r_;");
- pw.println("input dram_addr_a;");
- pw.println("output dram_isread_;");
- pw.println("output [63:0] dram_write_data_;");
- pw.println("output dram_write_data_push_;");
- pw.println("input dram_write_data_full;");
- pw.println("input [63:0] dram_read_data;");
- pw.println("output dram_read_data_pop_;");
- pw.println("input dram_read_data_empty;");
- pw.println("input [1:0] dram_read_data_latency;");
- }
- if (filename.equals("ddr2")) {
- pw.println("output [31:0] ddr2_addr_;");
- pw.println("output ddr2_addr_r_;");
- pw.println("input ddr2_addr_a;");
- pw.println("output ddr2_isread_;");
- pw.println("output [63:0] ddr2_write_data_;");
- pw.println("output ddr2_write_data_push_;");
- pw.println("input ddr2_write_data_full;");
- pw.println("input [63:0] ddr2_read_data;");
- pw.println("output ddr2_read_data_pop_;");
- pw.println("input ddr2_read_data_empty;");
- pw.println("input [1:0] ddr2_read_data_latency;");
- }
- if (filename.equals("video")) {
- pw.println("input vga_clk;");
- pw.println("output vga_psave;");
- pw.println("output vga_hsync;");
- pw.println("output vga_vsync;");
- pw.println("output vga_sync;");
- pw.println("output vga_blank;");
- pw.println("output [7:0] vga_r;");
- pw.println("output [7:0] vga_g;");
- pw.println("output [7:0] vga_b;");
- pw.println("output vga_clkout;");
+ for(PercolatedPort pp : sd.percolatedPorts) {
+ pw.print(pp.up ? "output" : "input");
+ pw.print(" ");
+ if (pp.width > 1)
+ pw.print("["+(pp.width-1)+":0]");
+ pw.print(" ");
+ pw.print(pp.name);
+ pw.println(";");
}
for(DockDescription bb : sd) {
}
pw.println();
}
+ if (filename.equals("debug")) {
+ String bb_name = "out";
+ pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
+ pw.println(" input "+bb_name+"_a;");
+ pw.println(" output "+bb_name+"_r_;");
+ pw.println(" reg "+bb_name+"_r;");
+ pw.println(" initial "+bb_name+"_r = 0;");
+ pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
+ }
- pw.println(sd.getSection("fpga"));
+ if (filename.equals("fifo")) {
+ pw.println(" wire in_a__;");
+ pw.println(" wire out_r__;");
+ pw.println(" fifo8x37 fifo8x37(clk, rst,");
+ pw.println(" in_r, in_a__, in_d,");
+ pw.println(" out_r__, out_a, out_d_);");
+ pw.println(" always @(posedge clk) begin");
+ pw.println(" if (!rst) begin");
+ pw.println(" `reset");
+ pw.println(" end else begin");
+ pw.println(" `flush");
+ pw.println(" out_r <= out_r__;");
+ pw.println(" in_a <= in_a__;");
+ pw.println(" end");
+ pw.println(" end");
+ } else {
+ pw.println(sd.getSection("fpga"));
+ }
pw.println("endmodule");