public static void main(String[] s) throws Exception {
new Fpga(new Module("root")).top.dump(s[0]);
+ PrintWriter pw;
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/timescale.v")));
+ pw.println("`timescale 1ns / 10ps");
+ pw.close();
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
+ pw.println("`define BRAM_ADDR_WIDTH 14");
+ pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
+ pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
+ pw.println("`define BRAM_NAME bram14");
+ pw.println("`include \"bram.inc\"");
+ pw.close();
+
+ pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/vram.v")));
+ pw.println("`define BRAM_ADDR_WIDTH 19");
+ pw.println("`define BRAM_DATA_WIDTH 3");
+ pw.println("`define BRAM_SIZE (640*480)");
+ pw.println("`define BRAM_NAME vram");
+ pw.println("`include \"bram.inc\"");
+ pw.close();
}
+ public Module getVerilogModule() { return top; }
+
public FleetProcess run(Instruction[] instructions) {
try {
return new Client(this, "none", instructions);
} catch (Exception e) { throw new RuntimeException(e); }
}
+ public BitVector getDestAddr(Path path) {
+ return ((FpgaPath)path).toBitVector();
+ }
+
// Setup //////////////////////////////////////////////////////////////////////////////
public Ship createShip(String type, String name) throws IOException {
this.top = top;
debugShip = createShip("Debug", "debug");
- boolean small = false;
+ //boolean small = false;
+ boolean small = true;
createShip("Memory", "memory1");
if (small) {
- createShip("Fifo", "fifo");
- createShip("Alu", "alu");
+ for(int i=0; i<2; i++)
+ createShip("Fifo", "fifo"+i);
+ for(int i=0; i<2; i++)
+ createShip("Alu", "alu"+i);
+ createShip("Counter", "counter");
+ createShip("CarrySaveAdder", "csa1");
+ createShip("Rotator", "rotator");
+ createShip("Lut3", "lut");
} else {
- //createShip("Memory", "memory2");
- //createShip("Memory", "memory3");
+ createShip("Memory", "memory2");
+ createShip("Memory", "memory3");
- for(int i=0; i<5; i++)
+ for(int i=0; i<3; i++)
createShip("Alu", "alu"+i);
- for(int i=0; i<2; i++)
+ for(int i=0; i<1; i++)
createShip("Fifo", "fifo"+i);
- for(int i=0; i<13; i++)
+ for(int i=0; i<14; i++)
createShip("Counter", "counter"+i);
+ /*
createShip("CarrySaveAdder", "csa1");
createShip("Rotator", "rotator");
createShip("Lut3", "lut");
-
+ */
//createShip("DDR2", "ddr2");
}
createShip("DRAM", "dram");
dests.addAll(outbox_dests);
top_horn = mkNode((FabricElement[])dests.toArray(new FabricElement[0]), true);
FabricElement source = mkNode((FabricElement[])sources.toArray(new FabricElement[0]), false);
- FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(top, null, source.getOutputPort());
+ FunnelModule.FunnelInstance top_funnel = new FunnelModule.FunnelInstance(this, top, null, source.getOutputPort());
((FunnelModule.FunnelInstance)source).out = top_funnel;
//top_horn.addInput(top_funnel, top_funnel.getOutputPort());
top_funnel.addOutput(top_horn, top_horn.getInputPort());
FabricElement leftPort = mkNode(ports, is_horn, start, (end+start)/2);
FabricElement rightPort = mkNode(ports, is_horn, (end+start)/2, end);
return is_horn
- ? new HornModule.HornInstance(top, leftPort, rightPort)
- : new FunnelModule.FunnelInstance(top, leftPort, rightPort);
+ ? new HornModule.HornInstance(this, top, leftPort, rightPort)
+ : new FunnelModule.FunnelInstance(this, top, leftPort, rightPort);
}
}
}
- public Module getVerilogModule() { return top; }
-
// Expand //////////////////////////////////////////////////////////////////////////////
pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
if (dd.isInputDock()) {
- pw.println("`define drain_"+name+" "+name+"_a <= 1");
+ pw.println("`define drain_"+name+" "+name+"_a <= 1;");
} else {
- pw.println("`define fill_"+name+" "+name+"_r <= 1");
+ pw.println("`define fill_"+name+" "+name+"_r <= 1;");
+ pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
}
}
+ if (debug) {
+ String name = "out";
+ pw.println("`define "+name+"_full ("+name+"_r && !"+name+"_a)");
+ pw.println("`define "+name+"_empty (!"+name+"_r && !"+name+"_a)");
+ pw.println("`define fill_"+name+" "+name+"_r <= 1;");
+ pw.println("`define "+name+"_draining ("+name+"_r && "+name+"_a)");
+ }
pw.print("`define reset ");
for(DockDescription bb : sd) {
if (bb.isInputDock()) pw.print(bb_name+"_a <= 1; "+bb_name+"_f <= 0; ");
else pw.print(bb_name+"_r <= 0; ");
}
+ if (debug) {
+ String bb_name = "out";
+ pw.print(bb_name+"_r <= 0; ");
+ }
+ pw.println();
+
+ pw.print("`define cleanup ");
+ for(DockDescription bb : sd) {
+ String bb_name = bb.getName();
+ if (bb.isInputDock()) pw.print("if (!"+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_a <= 0; ");
+ else pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
+ }
+ if (debug) {
+ String bb_name = "out";
+ pw.print("if ( "+bb_name+"_r && "+bb_name+"_a) "+bb_name+"_r <= 0; ");
+ }
pw.println();
+ // FIXME: this corresponds to something
+ /*
+ pw.print("`define flush_happening (1");
+ for(DockDescription bb : sd)
+ if (bb.isInputDock())
+ pw.print(" && "+bb.getName()+"_r_ && !"+bb.getName()+"_a && "+bb.getName()+"_d["+WIDTH_WORD+"]");
+ pw.println(")");
+ */
+
pw.print("`define flush ");
for(DockDescription bb : sd)
if (bb.isInputDock())
pw.println();
pw.println(" input clk;");
pw.println(" input rst;");
- if (filename.equals("debug")) {
- pw.println(" output ["+WIDTH_WORD+":0] out_d_;");
- pw.println(" input out_a;");
- pw.println(" output out_r_;");
- }
if (filename.equals("dram")) {
pw.println("output [31:0] dram_addr_;");
pw.println("output dram_addr_r_;");
}
pw.println();
}
+ if (filename.equals("debug")) {
+ String bb_name = "out";
+ pw.println(" output ["+WIDTH_WORD+":0] "+bb_name+"_d_;");
+ pw.println(" input "+bb_name+"_a;");
+ pw.println(" output "+bb_name+"_r_;");
+ pw.println(" reg "+bb_name+"_r;");
+ pw.println(" initial "+bb_name+"_r = 0;");
+ pw.println(" assign "+bb_name+"_r_ = "+bb_name+"_r;");
+ }
- pw.println(sd.getSection("fpga"));
+ if (filename.equals("fifo")) {
+ pw.println(" wire in_a__;");
+ pw.println(" wire out_r__;");
+ pw.println(" fifo8x37 fifo8x37(clk, rst,");
+ pw.println(" in_r, in_a__, in_d,");
+ pw.println(" out_r__, out_a, out_d_);");
+ pw.println(" always @(posedge clk) begin");
+ pw.println(" if (!rst) begin");
+ pw.println(" `reset");
+ pw.println(" end else begin");
+ pw.println(" `flush");
+ pw.println(" out_r <= out_r__;");
+ pw.println(" in_a <= in_a__;");
+ pw.println(" end");
+ pw.println(" end");
+ } else {
+ pw.println(sd.getSection("fpga"));
+ }
pw.println("endmodule");
} catch (Exception e) { throw new RuntimeException(e); }
}
- public long getDestAddr(Path path) {
- return ((FpgaPath)path).toLong();
- }
- public Dock getBoxByInstAddr(long dest) {
- for(Ship ship : Fpga.this)
- for(Dock bb : ship)
- if (((FpgaDestination)((FpgaDock)bb).getInstructionDestination()).getAddr() == dest)
- return bb;
- return null;
- }
-
}
projects / fleet.git / blobdiff