replace DATAWIDTH with WORDWIDTH

[fleet.git] / src / edu / berkeley / fleet / fpga / Fpga.java

diff --git a/src/edu/berkeley/fleet/fpga/Fpga.java b/src/edu/berkeley/fleet/fpga/Fpga.java
index b2cfd92..eb33e10 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/Fpga.java
+++ b/src/edu/berkeley/fleet/fpga/Fpga.java
@@ -20,8 +20,6 @@ import static edu.berkeley.fleet.fpga.verilog.Verilog.*;
 => clean up fabricelement methods
 => get rid of addcrap
 => automatic width-setting on ports
-=> nuke DATAWIDTH?
-  => serdes and fastclock/slowclock?
 */
 
 public class Fpga extends FleetTwoFleet {
@@ -51,7 +49,7 @@ public class Fpga extends FleetTwoFleet {
 
         pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(s[0]+"/bram14.v")));
         pw.println("`define BRAM_ADDR_WIDTH 14");
-        pw.println("`define BRAM_DATA_WIDTH `DATAWIDTH");
+        pw.println("`define BRAM_DATA_WIDTH `WORDWIDTH");
         pw.println("`define BRAM_SIZE (1<<(`BRAM_ADDR_WIDTH))");
         pw.println("`define BRAM_NAME bram14");
         pw.println("`include \"bram.inc\"");
@@ -234,7 +232,7 @@ public class Fpga extends FleetTwoFleet {
 
             boolean debug = "debug".equals(filename);
 
-            pw.println("`define DATAWIDTH                "+WIDTH_WORD);
+            pw.println("`define WORDWIDTH                "+WIDTH_WORD);
             pw.println("`define CODEBAG_SIZE_BITS        "+CBD_SIZE.valmaskwidth);
             pw.println();