import edu.berkeley.fleet.two.*;
import java.util.*;
-/** the pump itself is a */
public class FpgaDock extends FleetTwoDock implements FabricElement {
- private static final int INSTRUCTION_FIFO_SIZE = 12;
- private static final int EPILOGUE_FIFO_SIZE = 0;
- private static final int DATA_FIFO_SIZE = 4;
+ //private static final int INSTRUCTION_FIFO_SIZE = 12;
+
+ // Marina has 12 latches in the ring, 9 of which are wagged (plus
+ // M1, OD, RQ), so max capacity is 11 instructions
+ static final int INSTRUCTION_FIFO_SIZE = 11;
+ static final int INSTRUCTION_WAGGED_STAGES = 8;
+
+ //private static final int DATA_FIFO_SIZE = 4;
+ static final int DATA_FIFO_SIZE = 8;
private FpgaDestination dataDestination;
private FpgaDestination instructionDestination;
private FabricElement upstream;
public Module.SourcePort getOutputPort() { throw new RuntimeException(); }
public Module.Port getInputPort() { throw new RuntimeException(); }
- public FpgaPath getPath(FabricElement dest, BitVector signal) { return upstream.getPath((FabricElement)dest, signal); }
- public FpgaPath getPath(Destination dest,BitVector signal) { return upstream.getPath((FabricElement)dest, signal); }
+ public Path getPath(Destination dest,BitVector signal) { return getPath((FpgaDestination)dest, signal); }
+ public FpgaPath getPath(FpgaDestination dest,BitVector signal) { return upstream.getPath(dest, signal); }
+ public int getPathLength(FpgaDestination dest) { return upstream.getPathLength(dest)-1; }
public void addInput(FabricElement in, Module.Port inPort) { throw new RuntimeException(); }
public void addOutput(FabricElement out, Module.Port outPort) {
this.upstream = out;
public TorpedoBranchModule() {
super("torpedobranch");
Module.SourcePort in = createInputPort ("in", fpga.WIDTH_PACKET);
- // FIXME: assumes DISPATCH_PATH is at top of word!!!
- Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, "");
- Module.SinkPort torpedo = createOutputPort("torpedo", 0, "");
- in.hasLatch = false;
- out.hasLatch = false;
- torpedo.hasLatch = false;
-
- addPreCrap("assign out = "+fpga.PACKET_DATA.verilogVal("in")+";");
- addPreCrap("assign out_r = in_r && !("+fpga.PACKET_TOKEN.verilogVal("in")+");");
- addPreCrap("assign torpedo_r = in_r && "+fpga.PACKET_TOKEN.verilogVal("in")+";");
- addPreCrap("assign in_a = out_a || torpedo_a;");
+ Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module.SinkPort torpedo = createOutputPort("torpedo", 0);
+ Module.StateWire busy = new StateWire("busy", false);
+
+ new Event(new Object[] { in, busy.isFull(), out },
+ new Action[] { in, busy.doDrain() });
+ new Event(new Object[] { in, busy.isEmpty(), out, torpedo, in.testMask(fpga.PACKET_IS_TOKEN) },
+ new Action[] { in, torpedo });
+ new Event(new Object[] { in, busy.isEmpty(), out, in.testMask(fpga.PACKET_IS_TOKEN).invert() },
+ new Action[] { busy.doFill(), out });
+
+ out.connectValue(in.getBits(fpga.PACKET_DATA));
}
}
public class RequeueModule extends Module {
public RequeueModule() {
super("requeue");
- Module.SourcePort fabric_in = createInputPort ("fabric_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
- Module.SourcePort ondeck_in = createInputPort ("ondeck_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
- Module.SourcePort olc_in = createInputPort ("olc_in", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth);
- Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, "");
- out.forceNoLatch = true;
+ Module.SourcePort fabric_in = createInputPort ("fabric_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module.SourcePort ondeck_in = createInputPort ("ondeck_in", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module.SourcePort abort = createInputPort ("abort", 1);
+ Module.SinkPort out = createOutputPort("out", fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
- Module.StateWire using = new StateWire("using", false);
Module.StateWire circulating = new StateWire("circulating", false);
Module.StateWire doResetFabric = new StateWire("doResetFabric", false);
Module.StateWire doResetOndeck = new StateWire("doResetOndeck", false);
- addPreCrap("assign out = "+circulating.isEmpty()+" ? "+fabric_in.getName()+" : "+ondeck_in.getName()+";");
+ out.connectValue(new MuxValue(circulating.isEmpty(), fabric_in, ondeck_in));
// always: discard one-shot instructions
- new Event(new Object[] { ondeck_in, /*olc_in,*/ fpga.OS.verilog(ondeck_in.getName()) },
- new Action[] { ondeck_in, /*olc_in */});
-
new Event(new Object[] { doResetFabric.isFull(), out },
new Action[] { doResetFabric.doDrain(), fabric_in });
new Event(new Object[] { doResetOndeck.isFull(), out },
new Action[] { doResetOndeck.doDrain(), ondeck_in });
- new Event(new Object[] { circulating.isEmpty(), fabric_in, fpga.TAIL.verilog(fabric_in.getName()) },
- new Action[] { circulating.doFill(), fabric_in });
- new Event(new Object[] { circulating.isEmpty(), fabric_in, "!("+fpga.TAIL.verilog(fabric_in.getName())+")", doResetFabric.isEmpty() },
- new Action[] { out, doResetFabric.doFill() });
- new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
- new Action[] { ondeck_in, /*olc_in */ });
- new Event(new Object[] { using.isEmpty(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in!=0" },
- new Action[] { using.doFill() });
- new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in==0" },
- new Action[] { circulating.doDrain(), using.doDrain(), ondeck_in, /*olc_in */});
- new Event(new Object[] { circulating.isFull(), using.isFull(), ondeck_in, /*olc_in,*/ "!("+fpga.OS.verilog(ondeck_in.getName())+")", "olc_in!=0", doResetOndeck.isEmpty() },
- new Action[] { out, /*olc_in,*/ doResetOndeck.doFill() });
-
+ // Updating->Circulating transition
+ new Event(new Object[] { doResetFabric.isEmpty(),
+ doResetOndeck.isEmpty(),
+ circulating.isEmpty(),
+ fabric_in,
+ fpga.TAIL.verilog(fabric_in.getName()),
+ ondeck_in,
+ fpga.HEAD.verilog(ondeck_in.getName()) },
+ new Action[] { circulating.doFill(),
+ fabric_in,
+ ondeck_in });
+
+ // Circulating->Updating transition
+ new Event(new Object[] { doResetFabric.isEmpty(),
+ doResetOndeck.isEmpty(),
+ circulating.isFull(),
+ ondeck_in,
+ abort.getVerilog() },
+ new Action[] { circulating.doDrain(),
+ ondeck_in });
+
+ // Updating
+ new Event(new Object[] { doResetFabric.isEmpty(),
+ doResetOndeck.isEmpty(),
+ circulating.isEmpty(),
+ fabric_in,
+ "!"+fpga.TAIL.verilog(fabric_in.getName()) },
+ new Action[] { doResetFabric.doFill(),
+ out });
+ new Event(new Object[] { doResetFabric.isEmpty(),
+ doResetOndeck.isEmpty(),
+ circulating.isEmpty(),
+ ondeck_in,
+ "!"+fpga.HEAD.verilog(ondeck_in.getName()) },
+ new Action[] { ondeck_in });
+
+ // Circulating
+ new Event(new Object[] { doResetFabric.isEmpty(),
+ doResetOndeck.isEmpty(),
+ circulating.isFull(),
+ ondeck_in,
+ "!"+abort.getVerilog() },
+ new Action[] { doResetOndeck.doFill(),
+ out });
}
}
int dfifo_width = inbox ? fpga.getWordWidth()+1 : 1;
// FIXME: assumes fpga.DISPATCH_PATH is at top of word!!!
- Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module ififo_m_1 = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ //Module ififo_m_1 = new FifoModule(INSTRUCTION_FIFO_SIZE-INSTRUCTION_WAGGED_STAGES, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ //Module ififo_m_2 = new FifoModule(INSTRUCTION_WAGGED_STAGES, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, true);
+
Module dfifo_m = new FifoModule(DATA_FIFO_SIZE, dfifo_width);
Module.SourcePort instruction = createInputPort("instruction", fpga.WIDTH_PACKET);
Module.SourcePort fabric_in = createInputPort("fabric_in", fpga.WIDTH_PACKET);
// FIXME: at inboxes, no need for a full set of latches
- Module.SinkPort fabric_out = createOutputPort("fabric_out", fpga.WIDTH_PACKET, "");
+ Module.SinkPort fabric_out = createOutputPort("fabric_out", fpga.WIDTH_PACKET);
Module.InstantiatedModule dfifo = new Module.InstantiatedModule(this, dfifo_m);
- fabric_in.hasLatch = false;
fabric_in.connect(dfifo.getInputPort("in"));
- dfifo.getInputPort("in").noDriveLatches = true;
- if (inbox)
- addPreCrap("assign "+dfifo.getInputPort("in").getName()+
- " = { "+fpga.PACKET_SIGNAL.verilogVal("fabric_in")+
- ", "+fpga.PACKET_DATA.verilogVal("fabric_in")+" };\n");
- else
- addPreCrap("assign "+dfifo.getInputPort("in").getName()+
- " = "+fpga.PACKET_SIGNAL.verilogVal("fabric_in")+";\n");
-
+ dfifo.getInputPort("in").connectValue(
+ !inbox
+ ? fabric_in.getBits(fpga.PACKET_SIGNAL)
+ : new CatValue(new Value[] {
+ fabric_in.getBits(fpga.PACKET_SIGNAL),
+ fabric_in.getBits(fpga.PACKET_DATA)
+ }));
- Module.SourcePort dfifo_out = dfifo.getOutputPort("out");
- Module.SourcePort ship_out = null;
- if (!inbox) {
- ship_out = createInputPort("ship", fpga.getWordWidth()+1);
- ship_out.hasLatch = true;
- }
-
- Module.SinkPort ship_in = null;
- if (inbox) {
- ship_in = createOutputPort("ship", fpga.getWordWidth()+1, "");
- ship_in.hasLatch = true;
- }
+ Module.SourcePort dfifo_out = dfifo.getOutputPort("out");
+ Module.SourcePort ship_out = !inbox ? createInputPort("ship", fpga.getWordWidth()+1) : null;
+ Module.SinkPort ship_in = inbox ? createOutputPort("ship", fpga.getWordWidth()+1) : null;
Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
- Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
+ Module.Latch olc = new Latch("olc", fpga.getWordWidth(), 1);
Module.Latch flag_a = new Latch("flag_a", 1);
Module.Latch flag_b = new Latch("flag_b", 1);
Module.Latch flag_c = new Latch("flag_c", 1);
- Module.Latch flag_z = new Latch("flag_z", 1);
+ Module.Latch flag_d = new Latch("flag_d", 1);
- Module.StateWire torpedoWaiting = new StateWire("torpedoWaiting", false);
-
Module.SinkPort token_out = fabric_out;
Module.SourcePort token_in = dfifo_out;
Module.SinkPort data_out = inbox ? ship_in : fabric_out;
Module.SourcePort data_in = inbox ? dfifo_out : ship_out;
- Module.InstantiatedModule ififo = new Module.InstantiatedModule(this, ififo_m);
- Module.SinkPort ififo_in = ififo.getInputPort("in");
- Module.SourcePort ififo_out = ififo.getOutputPort("out");
-
- Module.SinkPort data_latch_output_p = createWirePort("data_latch_output", inbox ? fpga.getWordWidth()+1 : fpga.getWordWidth());
+ Module.InstantiatedModule ififo_1 = new Module.InstantiatedModule(this, ififo_m_1);
+ //Module.InstantiatedModule ififo_2 = new Module.InstantiatedModule(this, ififo_m_2);
+ //ififo_1.getOutputPort("out").connect(ififo_2.getInputPort("in"));
+ Module.SinkPort ififo_in = ififo_1.getInputPort("in");
+ //Module.SourcePort ififo_out = ififo_2.getOutputPort("out");
+ Module.SourcePort ififo_out = ififo_1.getOutputPort("out");
Module.InstantiatedModule torpedo_branch = new Module.InstantiatedModule(this, new TorpedoBranchModule());
instruction.connect(torpedo_branch.getInputPort("in"));
Module.InstantiatedModule requeue_module = new Module.InstantiatedModule(this, new RequeueModule());
Module.SinkPort requeue_fabric_in = requeue_module.getInputPort("fabric_in");
Module.SinkPort requeue_ondeck = requeue_module.getInputPort("ondeck_in");
- Module.SinkPort requeue_olc_in = requeue_module.getInputPort("olc_in");
+ Module.SinkPort requeue_abort = requeue_module.getInputPort("abort");
Module.SourcePort requeue_out = requeue_module.getOutputPort("out");
efifo_out.connect(requeue_fabric_in);
fanout_module_out0.connect(requeue_ondeck);
Module.SourcePort ondeck = fanout_module_out1;
- addPreCrap("assign data_latch_output = " + (inbox ? data_out.getName() : fpga.PACKET_DATA.verilogVal(data_out.getName()))+";");
- addPreCrap("wire ["+(Math.max(ilc.width,olc.width)-1)+":0] decremented;");
- addPreCrap("assign decremented = ("+fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName())+" ? {1'b0, olc} : ilc)-1;");
- addPreCrap("assign "+requeue_olc_in.getName()+" = olc;");
+ WireValue decremented = new WireValue("decremented", Math.max(ilc.width,olc.width),
+ new SimpleValue("("+ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE).getVerilogTrigger()+
+ " ? olc : ilc)-1"));
+ WireValue data_latch_output_p = new WireValue("data_latch_output",
+ inbox ? fpga.getWordWidth()+1 : fpga.getWordWidth(),
+ (inbox
+ ? new SimpleValue(data_out.getName())
+ : new SimpleValue(data_out.getBits(fpga.PACKET_DATA).getVerilog()))
+ );
- Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : fpga.PACKET_DATA.verilogVal(data_out.getName()));
- String data_latch_input = inbox ? data_in.getName() : data_in.getName();
+ Assignable data_latch = new SimpleAssignable(inbox ? data_out.getName() : data_out.getBits(fpga.PACKET_DATA).getVerilog());
+ Module.SourcePort data_latch_input = inbox ? data_in : data_in;
- String magic_standing_value = "(1<<"+fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+")";
- String done_executing = "(ilc==0 || ilc==1 || !"+fpga.MOVE.verilog(ondeck.getName())+")";
+ BitVector bv = new BitVector(fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1);
+ bv.set(fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth, true);
+ Value magic_standing_value = new ConstantValue(bv);
- // Torpedo Arrival
- new Event(new Object[] { torpedo_branch_torpedo, torpedoWaiting.isEmpty() },
- new Action[] { torpedo_branch_torpedo, torpedoWaiting.doFill() });
+ Trigger done_executing = new SimpleTrigger("((ilc==0) || (ilc==1) || !"+fpga.MOVE.verilog(ondeck.getName())+")");
String predicate_met =
"("+
"("+
- "!"+fpga.MOVE.verilog(ondeck.getName())+" || ilc!=0"+
+ "!"+fpga.MOVE.verilog(ondeck.getName())+" || (ilc!=0)"+
") && ("+
"("+
fpga.P_ALWAYS.verilog(ondeck.getName())+
") || ("+
- fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==flag_z"+
+ fpga.P_OLC_ZERO.verilog(ondeck.getName())+"==flag_d"+
")"+
") && ("+
" " + fpga.P_A.verilog(ondeck.getName())+" ? flag_a"+
")"+
")";
+ requeue_abort.connectValue(new SimpleValue("("+predicate_met+") && "+fpga.ABORT.verilog(ondeck.getName())));
+
// Torpedo strikes
new Event(new Object[] {
ondeck,
predicate_met,
fpga.MOVE.verilog(ondeck.getName()),
"!"+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName()),
- torpedoWaiting.isFull()
+ torpedo_branch_torpedo
},
new Object[] {
ondeck,
- torpedoWaiting.doDrain(),
- new AssignAction(olc, "0"),
- new AssignAction(flag_z, "1"),
- new AssignAction(ilc, "1")
+ torpedo_branch_torpedo,
+ new AssignAction(olc, new ConstantValue(new BitVector(olc.width).set(0))),
+ new AssignAction(flag_d, new ConstantValue(new BitVector(1).set(1))),
+ new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))
});
// Predicate not met
new Event(new Object[] { ondeck, "!("+predicate_met+")" },
new Action[] { ondeck,
- new ConditionalAction(fpga.MOVE.verilog(ondeck.getName()), new AssignAction(ilc, "1"))
+ new ConditionalAction(ondeck.testMask(fpga.MOVE),
+ new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1))))
});
new Event(new Object[] { ondeck,
data_out,
token_out,
predicate_met,
- "(!"+fpga.MOVE.verilog(ondeck.getName())+" || "+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName())+" || !"+torpedoWaiting.isFull()+")",
- new ConditionalTrigger(fpga.DI.verilog(ondeck.getName()), data_in),
- new ConditionalTrigger(fpga.TI.verilog(ondeck.getName()), token_in)
+ "(!"+fpga.MOVE.verilog(ondeck.getName())+" || "+fpga.NOT_INTERRUPTIBLE.verilog(ondeck.getName())+" || !"+torpedo_branch_torpedo.isFull()+")",
+ new ConditionalTrigger(ondeck.testMask(fpga.DI), data_in),
+ new ConditionalTrigger(ondeck.testMask(fpga.TI), token_in)
},
new Action[] {
- new ConditionalAction(done_executing+" && "+fpga.MOVE.verilog(ondeck.getName()), new AssignAction(ilc, "1")),
+ new ConditionalAction(new AndTrigger(done_executing, ondeck.testMask(fpga.MOVE)),
+ new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))),
new ConditionalAction(done_executing, ondeck),
- new ConditionalAction("!"+done_executing,
- new AssignAction(ilc,
- "ilc=="+magic_standing_value+"?"+magic_standing_value+":decremented")),
-
- new ConditionalAction(fpga.SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(olc, "data_latch_output")),
- new ConditionalAction(fpga.SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()),
- new AssignAction(olc, fpga.SET_OLC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
- new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()),
- new AssignAction(olc, "olc==0 ? 0 : decremented")),
-
- new ConditionalAction(fpga.SET_OLC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(flag_z, "0")),
- new ConditionalAction(fpga.SET_OLC_FROM_IMMEDIATE.verilog(ondeck.getName()), new AssignAction(flag_z, "0")),
- new ConditionalAction(fpga.SET_OLC_FROM_OLC_MINUS_ONE.verilog(ondeck.getName()), new AssignAction(flag_z, "(olc==0 || olc==1)")),
-
- new ConditionalAction(fpga.SET_ILC_FROM_DATA_LATCH.verilog(ondeck.getName()), new AssignAction(ilc, "data_latch_output")),
- new ConditionalAction(fpga.SET_ILC_FROM_IMMEDIATE.verilog(ondeck.getName()),
- new AssignAction(ilc, fpga.SET_ILC_FROM_IMMEDIATE.verilogVal(ondeck.getName()))),
- new ConditionalAction(fpga.SET_ILC_FROM_INFINITY.verilog(ondeck.getName()), new AssignAction(ilc, magic_standing_value)),
- new ConditionalAction(fpga.SHIFT.verilog(ondeck.getName()),
+ new ConditionalAction(done_executing.invert(),
+ new AssignAction(ilc, new MuxValue(new TestValue(ilc, TestValue.TestType.EQ, magic_standing_value),
+ magic_standing_value,
+ decremented.getBits(ilc.width-1,0)))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
+ new AssignAction(olc, new SimpleValue("data_latch_output"))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
+ new AssignAction(olc, ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
+ new AssignAction(olc, new SimpleValue("olc==0 ? 0 : decremented"))),
+
+ new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
+ new AssignAction(flag_d, new SimpleValue("data_latch_output==0"))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
+ new AssignAction(flag_d, new SimpleValue(ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE).getVerilog()+"==0"))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
+ new AssignAction(flag_d, new SimpleValue("(olc==0 || olc==1)"))),
+
+ new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_DATA_LATCH),
+ new AssignAction(ilc, new SimpleValue("data_latch_output"))),
+
+ new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_IMMEDIATE),
+ new AssignAction(ilc, ondeck.getBits(fpga.SET_ILC_FROM_IMMEDIATE))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_ILC_FROM_INFINITY),
+ new AssignAction(ilc, magic_standing_value)),
+ new ConditionalAction(ondeck.testMask(fpga.SHIFT),
new AssignAction(data_latch,
- "{ data_latch_output["+(fpga.getWordWidth()-1-fpga.SHIFT.valmaskwidth)+":0], "+
- fpga.SHIFT.verilogVal(ondeck.getName())+"}")),
- new ConditionalAction(fpga.SET_IMMEDIATE.verilog(ondeck.getName()),
+ new SimpleValue("{ data_latch_output["+(fpga.getWordWidth()-1-fpga.SHIFT.valmaskwidth)+":0], "+
+ ondeck.getBits(fpga.SHIFT).getVerilog()+"}"))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_IMMEDIATE),
new AssignAction(data_latch,
- "{ {"+(fpga.getWordWidth()-fpga.DataLatch_WIDTH)+
- "{"+fpga.SET_IMMEDIATE_EXTEND.verilogVal(ondeck.getName())+"}}, "+
- fpga.SET_IMMEDIATE.verilogVal(ondeck.getName())+" }")),
- new ConditionalAction(fpga.SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_a, new_flag(fpga.SET_FLAGS_A.verilogVal(ondeck.getName())))),
- new ConditionalAction(fpga.SET_FLAGS.verilog(ondeck.getName()), new AssignAction(flag_b, new_flag(fpga.SET_FLAGS_B.verilogVal(ondeck.getName())))),
- new ConditionalAction(inbox
- ? "("+fpga.DI.verilog(ondeck.getName())+" || "+fpga.TI.verilog(ondeck.getName())+")"
- : "(!"+fpga.DI.verilog(ondeck.getName())+" && "+fpga.TI.verilog(ondeck.getName())+")",
- new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))),
- new ConditionalAction(fpga.DI.verilog(ondeck.getName()), data_in),
- new ConditionalAction(fpga.DO.verilog(ondeck.getName()), data_out),
- new ConditionalAction(fpga.FLUSH.verilog(ondeck.getName()), data_out),
+ new SimpleValue("{ {"+(fpga.getWordWidth()-fpga.DataLatch_WIDTH)+
+ "{"+ondeck.getBits(fpga.SET_IMMEDIATE_EXTEND).getVerilog()+"}}, "+
+ ondeck.getBits(fpga.SET_IMMEDIATE).getVerilog()+" }"))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
+ new AssignAction(flag_a, new_flag(ondeck.getBits(fpga.SET_FLAGS_A),flag_a,flag_b,flag_c))),
+ new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
+ new AssignAction(flag_b, new_flag(ondeck.getBits(fpga.SET_FLAGS_B),flag_a,flag_b,flag_c))),
+ new ConditionalAction(ondeck.testMask(fpga.MOVE),
+ new AssignAction(flag_c,
+ inbox
+ ? dfifo_out.getBits(dfifo_width-1, dfifo_width-1)
+ : new MuxValue(ondeck.testMask(fpga.DC),
+ ship_out.getBits(fpga.getWordWidth(), fpga.getWordWidth()),
+ dfifo_out.getBits(dfifo_width-1, dfifo_width-1))
+ )),
+ new ConditionalAction(ondeck.testMask(fpga.DI), data_in),
+ new ConditionalAction(ondeck.testMask(fpga.DO), data_out),
+ new ConditionalAction(ondeck.testMask(fpga.FLUSH), data_out),
inbox
- ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"), fpga.FLUSH.verilog(ondeck.getName())+"?1:0")
- : new ConditionalAction(fpga.DI.verilog(ondeck.getName()), new AssignAction(flag_c, data_latch_input+"["+fpga.getWordWidth()+"]")),
- new ConditionalAction(fpga.TI.verilog(ondeck.getName()), token_in),
- new ConditionalAction(fpga.TO.verilog(ondeck.getName()), token_out),
- new ConditionalAction(fpga.DC.verilog(ondeck.getName()), new AssignAction(data_latch, data_latch_input)),
- new AssignAction(new SimpleAssignable(fpga.PACKET_TOKEN.verilogVal(token_out.getName())), "("+fpga.TO.verilog(ondeck.getName())+")?1:0"),
- new ConditionalAction(fpga.PATH_DATA.verilog(ondeck.getName()),
- new AssignAction(new SimpleAssignable("{ "+fpga.PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
- fpga.PACKET_DEST.verilogVal(token_out.getName())+" }"),
- fpga.DISPATCH_PATH.verilogVal(data_latch_input))),
- new ConditionalAction(fpga.PATH_IMMEDIATE.verilog(ondeck.getName()),
- new AssignAction(new SimpleAssignable("{ "+fpga.PACKET_SIGNAL.verilogVal(token_out.getName())+", "+
- fpga.PACKET_DEST.verilogVal(token_out.getName())+" }"),
- fpga.PATH_IMMEDIATE.verilogVal(ondeck.getName()))),
+ ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"),
+ new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
+ : null,
+ new ConditionalAction(ondeck.testMask(fpga.TI), token_in),
+ new ConditionalAction(ondeck.testMask(fpga.TO), token_out),
+ new ConditionalAction(ondeck.testMask(fpga.DC), new AssignAction(data_latch, data_latch_input)),
+ new AssignAction(token_out.getBits(fpga.PACKET_TOKEN),
+ new SimpleValue("("+fpga.TO.verilog(ondeck.getName())+")?1:0")),
+ new ConditionalAction(ondeck.testMask(fpga.PATH_DATA),
+ new AssignAction(new SimpleAssignable("{ "+token_out.getBits(fpga.PACKET_SIGNAL).getVerilog()+", "+
+ token_out.getBits(fpga.PACKET_DEST).getVerilog()+" }"),
+ data_latch_input.getBits(fpga.DISPATCH_PATH))),
+ new ConditionalAction(ondeck.testMask(fpga.PATH_IMMEDIATE),
+ new AssignAction(new SimpleAssignable("{ "+token_out.getBits(fpga.PACKET_SIGNAL).getVerilog()+", "+
+ token_out.getBits(fpga.PACKET_DEST).getVerilog()+" }"),
+ ondeck.getBits(fpga.PATH_IMMEDIATE)))
}
- );
+ );
}
- private String new_flag(String x) {
- return "("+
- "( (("+x+" >> 0) & 1) & !flag_c) |" +
- "( (("+x+" >> 1) & 1) & flag_c) |" +
- "( (("+x+" >> 2) & 1) & !flag_b) |" +
- "( (("+x+" >> 3) & 1) & flag_b) |" +
- "( (("+x+" >> 4) & 1) & !flag_a) |" +
- "( (("+x+" >> 5) & 1) & flag_a) | 0" +
- ")";
+ private Value new_flag(Value v, Value flag_a, Value flag_b, Value flag_c) {
+ Value[] vals = new Value[] {
+ new LogicValue(v.getBits(0,0), LogicValue.LogicType.AND, flag_c.invertBits()),
+ new LogicValue(v.getBits(1,1), LogicValue.LogicType.AND, flag_c),
+ new LogicValue(v.getBits(2,2), LogicValue.LogicType.AND, flag_b.invertBits()),
+ new LogicValue(v.getBits(3,3), LogicValue.LogicType.AND, flag_b),
+ new LogicValue(v.getBits(4,4), LogicValue.LogicType.AND, flag_a.invertBits()),
+ new LogicValue(v.getBits(5,5), LogicValue.LogicType.AND, flag_a),
+ };
+ Value ret = new ConstantValue(new BitVector(1).set(0));
+ for(int i=0; i<vals.length; i++)
+ ret = new LogicValue(ret, LogicValue.LogicType.OR, vals[i]);
+ return ret;
}
}
}
projects / fleet.git / blobdiff