public class FpgaDock extends FleetTwoDock implements FabricElement {
- private static final int INSTRUCTION_FIFO_SIZE = 12;
- private static final int EPILOGUE_FIFO_SIZE = 0;
- private static final int DATA_FIFO_SIZE = 4;
+ //private static final int INSTRUCTION_FIFO_SIZE = 12;
+
+ // Marina has 12 latches in the ring, 9 of which are wagged (plus
+ // M1, OD, RQ), so max capacity is 11 instructions
+ static final int INSTRUCTION_FIFO_SIZE = 11;
+ static final int INSTRUCTION_WAGGED_STAGES = 8;
+
+ //private static final int DATA_FIFO_SIZE = 4;
+ static final int DATA_FIFO_SIZE = 8;
private FpgaDestination dataDestination;
private FpgaDestination instructionDestination;
public Module.Port getInputPort() { throw new RuntimeException(); }
public Path getPath(Destination dest,BitVector signal) { return getPath((FpgaDestination)dest, signal); }
public FpgaPath getPath(FpgaDestination dest,BitVector signal) { return upstream.getPath(dest, signal); }
+ public int getPathLength(FpgaDestination dest) { return upstream.getPathLength(dest)-1; }
public void addInput(FabricElement in, Module.Port inPort) { throw new RuntimeException(); }
public void addOutput(FabricElement out, Module.Port outPort) {
this.upstream = out;
int dfifo_width = inbox ? fpga.getWordWidth()+1 : 1;
// FIXME: assumes fpga.DISPATCH_PATH is at top of word!!!
- Module ififo_m = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ Module ififo_m_1 = new FifoModule(INSTRUCTION_FIFO_SIZE, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ //Module ififo_m_1 = new FifoModule(INSTRUCTION_FIFO_SIZE-INSTRUCTION_WAGGED_STAGES, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth);
+ //Module ififo_m_2 = new FifoModule(INSTRUCTION_WAGGED_STAGES, fpga.getWordWidth()-fpga.DISPATCH_PATH.valmaskwidth, true);
+
Module dfifo_m = new FifoModule(DATA_FIFO_SIZE, dfifo_width);
Module.SourcePort instruction = createInputPort("instruction", fpga.WIDTH_PACKET);
Module.SinkPort ship_in = inbox ? createOutputPort("ship", fpga.getWordWidth()+1) : null;
Module.Latch ilc = new Latch("ilc", fpga.SET_ILC_FROM_IMMEDIATE.valmaskwidth+1, 1);
- Module.Latch olc = new Latch("olc", fpga.SET_OLC_FROM_IMMEDIATE.valmaskwidth, 1);
+ Module.Latch olc = new Latch("olc", fpga.getWordWidth(), 1);
Module.Latch flag_a = new Latch("flag_a", 1);
Module.Latch flag_b = new Latch("flag_b", 1);
Module.Latch flag_c = new Latch("flag_c", 1);
Module.Latch flag_d = new Latch("flag_d", 1);
- Module.Latch flag_z = new Latch("flag_z", 1);
Module.SinkPort token_out = fabric_out;
Module.SourcePort token_in = dfifo_out;
Module.SinkPort data_out = inbox ? ship_in : fabric_out;
Module.SourcePort data_in = inbox ? dfifo_out : ship_out;
- Module.InstantiatedModule ififo = new Module.InstantiatedModule(this, ififo_m);
- Module.SinkPort ififo_in = ififo.getInputPort("in");
- Module.SourcePort ififo_out = ififo.getOutputPort("out");
+ Module.InstantiatedModule ififo_1 = new Module.InstantiatedModule(this, ififo_m_1);
+ //Module.InstantiatedModule ififo_2 = new Module.InstantiatedModule(this, ififo_m_2);
+ //ififo_1.getOutputPort("out").connect(ififo_2.getInputPort("in"));
+ Module.SinkPort ififo_in = ififo_1.getInputPort("in");
+ //Module.SourcePort ififo_out = ififo_2.getOutputPort("out");
+ Module.SourcePort ififo_out = ififo_1.getOutputPort("out");
Module.InstantiatedModule torpedo_branch = new Module.InstantiatedModule(this, new TorpedoBranchModule());
instruction.connect(torpedo_branch.getInputPort("in"));
WireValue decremented = new WireValue("decremented", Math.max(ilc.width,olc.width),
new SimpleValue("("+ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE).getVerilogTrigger()+
- " ? {1'b0, olc} : ilc)-1"));
+ " ? olc : ilc)-1"));
WireValue data_latch_output_p = new WireValue("data_latch_output",
inbox ? fpga.getWordWidth()+1 : fpga.getWordWidth(),
(inbox
ondeck,
torpedo_branch_torpedo,
new AssignAction(olc, new ConstantValue(new BitVector(olc.width).set(0))),
- new AssignAction(flag_z, new ConstantValue(new BitVector(1).set(1))),
new AssignAction(flag_d, new ConstantValue(new BitVector(1).set(1))),
new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))
});
new ConditionalAction(done_executing.invert(),
new AssignAction(ilc, new MuxValue(new TestValue(ilc, TestValue.TestType.EQ, magic_standing_value),
magic_standing_value,
- decremented))),
+ decremented.getBits(ilc.width-1,0)))),
new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
new AssignAction(olc, new SimpleValue("data_latch_output"))),
new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
new AssignAction(olc, new SimpleValue("olc==0 ? 0 : decremented"))),
new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
- new AssignAction(flag_z, new ConstantValue(new BitVector(1).set(0)))),
- new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
- new AssignAction(flag_z, new ConstantValue(new BitVector(1).set(0)))),
- new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
- new AssignAction(flag_z, new SimpleValue("(olc==0 || olc==1)"))),
-
- new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
new AssignAction(flag_d, new SimpleValue("data_latch_output==0"))),
new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
new AssignAction(flag_d, new SimpleValue(ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE).getVerilog()+"==0"))),
projects / fleet.git / blobdiff