private static final int INSTRUCTION_FIFO_SIZE = 12;
private static final int EPILOGUE_FIFO_SIZE = 0;
- private static final int DATA_FIFO_SIZE = 4;
+ //private static final int DATA_FIFO_SIZE = 4;
+ private static final int DATA_FIFO_SIZE = 8;
private FpgaDestination dataDestination;
private FpgaDestination instructionDestination;
Module.Latch flag_b = new Latch("flag_b", 1);
Module.Latch flag_c = new Latch("flag_c", 1);
Module.Latch flag_d = new Latch("flag_d", 1);
- Module.Latch flag_z = new Latch("flag_z", 1);
Module.SinkPort token_out = fabric_out;
Module.SourcePort token_in = dfifo_out;
ondeck,
torpedo_branch_torpedo,
new AssignAction(olc, new ConstantValue(new BitVector(olc.width).set(0))),
- new AssignAction(flag_z, new ConstantValue(new BitVector(1).set(0))),
- new AssignAction(flag_d, new ConstantValue(new BitVector(1).set(0))),
+ new AssignAction(flag_d, new ConstantValue(new BitVector(1).set(1))),
new AssignAction(ilc, new ConstantValue(new BitVector(ilc.width).set(1)))
});
new AssignAction(olc, new SimpleValue("olc==0 ? 0 : decremented"))),
new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
- new AssignAction(flag_z, new ConstantValue(new BitVector(1).set(0)))),
- new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
- new AssignAction(flag_z, new ConstantValue(new BitVector(1).set(0)))),
- new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_OLC_MINUS_ONE),
- new AssignAction(flag_z, new SimpleValue("(olc==0 || olc==1)"))),
-
- new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_DATA_LATCH),
new AssignAction(flag_d, new SimpleValue("data_latch_output==0"))),
new ConditionalAction(ondeck.testMask(fpga.SET_OLC_FROM_IMMEDIATE),
new AssignAction(flag_d, new SimpleValue(ondeck.getBits(fpga.SET_OLC_FROM_IMMEDIATE).getVerilog()+"==0"))),
new AssignAction(flag_a, new_flag(ondeck.getBits(fpga.SET_FLAGS_A),flag_a,flag_b,flag_c))),
new ConditionalAction(ondeck.testMask(fpga.SET_FLAGS),
new AssignAction(flag_b, new_flag(ondeck.getBits(fpga.SET_FLAGS_B),flag_a,flag_b,flag_c))),
- new ConditionalAction(inbox
- ? new OrTrigger(ondeck.testMask(fpga.DI), ondeck.testMask(fpga.TI))
- : new AndTrigger(ondeck.testMask(fpga.DI).invert(), ondeck.testMask(fpga.TI)),
- new AssignAction(flag_c, dfifo_out.getBits(dfifo_width-1, dfifo_width-1))),
+ new ConditionalAction(ondeck.testMask(fpga.MOVE),
+ new AssignAction(flag_c,
+ inbox
+ ? dfifo_out.getBits(dfifo_width-1, dfifo_width-1)
+ : new MuxValue(ondeck.testMask(fpga.DC),
+ ship_out.getBits(fpga.getWordWidth(), fpga.getWordWidth()),
+ dfifo_out.getBits(dfifo_width-1, dfifo_width-1))
+ )),
new ConditionalAction(ondeck.testMask(fpga.DI), data_in),
new ConditionalAction(ondeck.testMask(fpga.DO), data_out),
new ConditionalAction(ondeck.testMask(fpga.FLUSH), data_out),
inbox
- ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"), new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
- : new ConditionalAction(ondeck.testMask(fpga.DI), new AssignAction(flag_c, new SimpleValue(data_latch_input.getVerilog()+"["+fpga.getWordWidth()+"]"))),
+ ? new AssignAction(new SimpleAssignable(data_out.getName()+"["+fpga.getWordWidth()+"]"),
+ new SimpleValue(fpga.FLUSH.verilog(ondeck.getName())+"?1:0"))
+ : null,
new ConditionalAction(ondeck.testMask(fpga.TI), token_in),
new ConditionalAction(ondeck.testMask(fpga.TO), token_out),
new ConditionalAction(ondeck.testMask(fpga.DC), new AssignAction(data_latch, data_latch_input)),