private static final int INSTRUCTION_FIFO_SIZE = 12;
private static final int EPILOGUE_FIFO_SIZE = 0;
//private static final int DATA_FIFO_SIZE = 4;
- private static final int DATA_FIFO_SIZE = 8;
+ static final int DATA_FIFO_SIZE = 8;
private FpgaDestination dataDestination;
private FpgaDestination instructionDestination;
public Module.Port getInputPort() { throw new RuntimeException(); }
public Path getPath(Destination dest,BitVector signal) { return getPath((FpgaDestination)dest, signal); }
public FpgaPath getPath(FpgaDestination dest,BitVector signal) { return upstream.getPath(dest, signal); }
+ public int getPathLength(FpgaDestination dest) { return upstream.getPathLength(dest)-1; }
public void addInput(FabricElement in, Module.Port inPort) { throw new RuntimeException(); }
public void addOutput(FabricElement out, Module.Port outPort) {
this.upstream = out;