private Module module;
private Module.InstantiatedModule instance;
private LinkedHashMap<String,FpgaDock> ports = new LinkedHashMap<String,FpgaDock>();
+ LinkedHashMap<String,Module.SourcePort> docklessPorts = new LinkedHashMap<String,Module.SourcePort>();
/** You should instantiate a bunch of Inboxes and Outboxes in your constructor */
public FpgaShip(Fpga fleet, ShipDescription sd) {
super(fleet, sd);
this.module = new Module(getType().toLowerCase());
this.instance = new Module.InstantiatedModule(fleet.getVerilogModule(), module);
- for(DockDescription sdbb : sd) {
- if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), getFleet().getWordWidth()+1);
- else module.createOutputPort(sdbb.getName(), getFleet().getWordWidth()+1, "");
- ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
+ for(DockDescription sdbb : sd.ports()) {
+ if (sdbb.isDockless()) {
+ module.createOutputPort(sdbb.getName(), fleet.WIDTH_PACKET);
+ docklessPorts.put(sdbb.getName(), instance.getOutputPort(sdbb.getName()));
+ } else {
+ if (sdbb.isInputDock()) module.createInputPort(sdbb.getName(), getFleet().getWordWidth()+1);
+ else module.createOutputPort(sdbb.getName(), getFleet().getWordWidth()+1);
+ ports.put(sdbb.getName(), new FpgaDock(this, sdbb));
+ }
}
- if (getType().toLowerCase().equals("debug"))
- module.createOutputPort("debug_out", getFleet().getWordWidth(), "");
for(PercolatedPort pp : sd.percolatedPorts)
this.module.percolatedPorts.add(pp);
}