-module `BRAM_NAME(clk, we, a, dpra, di, spo, dpo);
+/* bram.inc */
+module `BRAM_NAME(clk, rst, we, a, dpra, di, spo, dpo);
input clk;
+ input rst;
input we;
input [(`BRAM_ADDR_WIDTH-1):0] a;
input [(`BRAM_ADDR_WIDTH-1):0] dpra;
input [(`BRAM_DATA_WIDTH-1):0] di;
output [(`BRAM_DATA_WIDTH-1):0] spo;
output [(`BRAM_DATA_WIDTH-1):0] dpo;
- reg [(`BRAM_DATA_WIDTH-1):0] ram [((1<<(`BRAM_ADDR_WIDTH))-1):0];
+ reg [(`BRAM_DATA_WIDTH-1):0] ram [((`BRAM_SIZE)-1):0];
reg [(`BRAM_ADDR_WIDTH-1):0] read_a;
reg [(`BRAM_ADDR_WIDTH-1):0] read_dpra;
always @(posedge clk) begin
assign spo = ram[read_a];
assign dpo = ram[read_dpra];
endmodule
+/* bram.inc */