remove synthesis attributes that xst doesnt understand
[fleet.git] / src / edu / berkeley / fleet / fpga / ddr2 / ddr2_phy_dqs_iob.v
index a626f72..14e29b4 100644 (file)
@@ -93,7 +93,7 @@ module ddr2_phy_dqs_iob #
   wire                     dqs_oe_n_delay;
   wire                     dqs_oe_n_r;
   wire                     dqs_rst_n_delay;
-  reg                      dqs_rst_n_r /* synthesis syn_preserve = 1*/;
+  reg                      dqs_rst_n_r /* */;
   wire                     dqs_out;
   wire                     en_dqs_sync /* synthesis syn_keep = 1 */;
 
@@ -229,7 +229,7 @@ module ddr2_phy_dqs_iob #
      .Q   (dqs_oe_n_r),
      .C   (clk180),
      .PRE (rst0)
-     ) /* synthesis syn_useioff = 1 */;
+     ) /* */;
 
   //***************************************************************************