-######################################
-## System clock pins
-######################################
+############################################################################
+## This system.ucf file is generated by Base System Builder based on the
+## settings in the selected Xilinx Board Definition file. Please add other
+## user constraints to this file based on customer design specifications.
+############################################################################
-NET User_Clk PERIOD=100MHz;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTA LOC=P5;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTA IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTA TIG;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTB LOC=R8;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTB IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTB TIG;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTC LOC=P9;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTC IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTC TIG;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTD LOC=V4;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTD IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_PCI_INTD TIG;
+#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT LOC=AE21;
+#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT IOSTANDARD = LVCMOS25;
+#Net fpga_0_PCI32_BRIDGE_PCI_SBR_INT TIG;
+Net sys_clk_pin LOC=J16;
+Net sys_clk_pin IOSTANDARD = LVCMOS25;
+Net sys_rst_pin LOC=H7;
+Net sys_rst_pin PULLUP;
+Net sys_rst_pin IOSTANDARD = LVCMOS33;
+### System level constraints
+#Net sys_clk_pin TNM_NET = sys_clk_pin;
+#TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 10000 ps;
+#Net sys_rst_pin TIG;
+#NET "C405RSTCORERESETREQ" TPTHRU = "RST_GRP";
+#NET "C405RSTCHIPRESETREQ" TPTHRU = "RST_GRP";
+#NET "C405RSTSYSRESETREQ" TPTHRU = "RST_GRP";
+#TIMESPEC "TS_RST1" = FROM CPUS THRU RST_GRP TO FFS TIG;
+#Net fpga_0_PCI_CLK_FB LOC=H17;
+#Net fpga_0_PCI_CLK_FB IOSTANDARD = LVCMOS25;
+#Net fpga_0_PCI_CLK_FB TNM_NET = PCI_CLK;
+#Net PCI32_BRIDGE/OPB_Clk TNM_NET = SYS_CLK;
+##TIMESPEC TS_PCI_BUS = FROM PCI_CLK TO SYS_CLK 10000 ps;
+#TIMESPEC "TS_PCI_BUS" = FROM "PCI_CLK" TO "SYS_CLK" 9.9ns datapathonly;
+#TIMESPEC TS_BUS_PCI = FROM SYS_CLK TO PCI_CLK 30000 ps;
+#Net fpga_0_PCI_CLK_OUT0 LOC=V5;
+#Net fpga_0_PCI_CLK_OUT0 IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI_CLK_OUT1 LOC=T11;
+#Net fpga_0_PCI_CLK_OUT1 IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI_CLK_OUT2 LOC=U6;
+#Net fpga_0_PCI_CLK_OUT2 IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI_CLK_OUT3 LOC=U7;
+#Net fpga_0_PCI_CLK_OUT3 IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI_CLK_OUT4 LOC=U3;
+#Net fpga_0_PCI_CLK_OUT4 IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI_CLK_OUT5 LOC=U5;
+#Net fpga_0_PCI_CLK_OUT5 IOSTANDARD = PCI33_3;
+#Net fpga_0_DDR_CLK_FB LOC=K18;
+#Net fpga_0_DDR_CLK_FB IOSTANDARD = LVCMOS25;
+#
+### IO Devices constraints
+#
+##### Module RS232_Uart_1 constraints
+#
+Net fpga_0_RS232_Uart_1_ctsN_pin LOC=G6;
+Net fpga_0_RS232_Uart_1_ctsN_pin IOSTANDARD = LVCMOS33;
+Net fpga_0_RS232_Uart_1_ctsN_pin TIG;
+Net fpga_0_RS232_Uart_1_rtsN_pin LOC=F6;
+Net fpga_0_RS232_Uart_1_rtsN_pin IOSTANDARD = LVCMOS33;
+Net fpga_0_RS232_Uart_1_rtsN_pin TIG;
-NET Clkin_p LOC = AP21 | IOSTANDARD = LVDS_25;
-NET Clkin_m LOC = AN21 | IOSTANDARD = LVDS_25;
+Net fpga_0_RS232_Uart_1_sin_pin LOC=E6;
+Net fpga_0_RS232_Uart_1_sin_pin IOSTANDARD = LVCMOS33;
+Net fpga_0_RS232_Uart_1_sin_pin TIG;
+Net fpga_0_RS232_Uart_1_sin_pin PULLUP;
-######################################
-## SelectMAP interface pins
-######################################
+Net fpga_0_RS232_Uart_1_sout_pin LOC=D6;
+Net fpga_0_RS232_Uart_1_sout_pin IOSTANDARD = LVCMOS33;
+Net fpga_0_RS232_Uart_1_sout_pin TIG;
+Net fpga_0_RS232_Uart_1_sout_pin PULLUP;
-NET D_I<0> LOC = AU9 | IOSTANDARD = LVCMOS25;
-NET D_I<1> LOC = AV9 | IOSTANDARD = LVCMOS25;
-NET D_I<2> LOC = AY9 | IOSTANDARD = LVCMOS25;
-NET D_I<3> LOC = AW9 | IOSTANDARD = LVCMOS25;
-NET D_I<4> LOC = AW34 | IOSTANDARD = LVCMOS25;
-NET D_I<5> LOC = AY34 | IOSTANDARD = LVCMOS25;
-NET D_I<6> LOC = AV34 | IOSTANDARD = LVCMOS25;
-NET D_I<7> LOC = AU34 | IOSTANDARD = LVCMOS25;
-
-NET RDWR_B LOC = AR34 | IOSTANDARD = LVCMOS25;
-NET CS_B LOC = AT34 | IOSTANDARD = LVCMOS25;
-NET INIT_B LOC = AR9 | IOSTANDARD = LVCMOS25;
-NET CCLK LOC = C14 | IOSTANDARD = LVCMOS25;
-
-NET gpleds<1> LOC = AB6 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<2> LOC = AB7 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<3> LOC = AB9 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<4> LOC = AB10 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<5> LOC = AD7 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
-NET gpleds<6> LOC = AF1 | IOSTANDARD = LVCMOS18 | DRIVE = 24;
+##### Module DDR_SDRAM_32Mx64 constraints
+#
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> LOC=P24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<12> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> LOC=P22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<11> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> LOC=N22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<10> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> LOC=N23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<9> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> LOC=N24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<8> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> LOC=M23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<7> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> LOC=L24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<6> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> LOC=L25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<5> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> LOC=L26;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<4> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> LOC=K23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<3> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> LOC=K24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<2> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> LOC=K26;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<1> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> LOC=J24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Addr_pin<0> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> LOC=J25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<1> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> LOC=J26;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_BankAddr_pin<0> IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin LOC=D26;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CASn_pin IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin LOC=H14;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CKE_pin IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin LOC=C27;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_CSn_pin IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin LOC=D27;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_RASn_pin IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin LOC=E27;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_WEn_pin IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> LOC=G23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<0> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> LOC=E23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<1> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> LOC=G22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<2> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> LOC=F21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DM_pin<3> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> LOC=F25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<0> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> LOC=G25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<1> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> LOC=G20;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<2> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> LOC=F20;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQS_pin<3> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> LOC=E22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<0> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> LOC=E24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<1> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> LOC=H24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<2> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> LOC=H25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<3> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> LOC=G26;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<4> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> LOC=F26;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<5> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> LOC=F24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<6> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> LOC=F23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<7> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> LOC=C28;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<8> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> LOC=D25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<9> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> LOC=D24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<10> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> LOC=D22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<11> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> LOC=C25;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<12> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> LOC=C24;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<13> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> LOC=C23;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<14> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> LOC=C22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<15> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> LOC=H22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<16> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> LOC=J22;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<17> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> LOC=L21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<18> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> LOC=K21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<19> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> LOC=J21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<20> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> LOC=J20;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<21> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> LOC=H20;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<22> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> LOC=G21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<23> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> LOC=E21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<24> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> LOC=D21;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<25> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> LOC=E19;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<26> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> LOC=F19;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<27> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> LOC=G18;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<28> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> LOC=F18;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<29> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> LOC=E18;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<30> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> LOC=E17;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_DQ_pin<31> IOSTANDARD = SSTL2_II;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin LOC=F28;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clk_pin IOSTANDARD = SSTL2_I;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin LOC=E28;
+#Net fpga_0_DDR_SDRAM_32Mx64_DDR_Clkn_pin IOSTANDARD = SSTL2_I;
+#
+##### Module SPI_EEPROM constraints
+#
+#Net fpga_0_SPI_EEPROM_SCK_pin LOC=AF21;
+#Net fpga_0_SPI_EEPROM_SCK_pin IOSTANDARD = LVCMOS25;
+#Net fpga_0_SPI_EEPROM_SCK_pin TIG;
+#Net fpga_0_SPI_EEPROM_SCK_pin PULLUP;
+#Net fpga_0_SPI_EEPROM_MOSI_pin LOC=AH22;
+#Net fpga_0_SPI_EEPROM_MOSI_pin TIG;
+#Net fpga_0_SPI_EEPROM_MOSI_pin PULLUP;
+#Net fpga_0_SPI_EEPROM_MISO_pin LOC=AJ22;
+#Net fpga_0_SPI_EEPROM_MISO_pin TIG;
+#Net fpga_0_SPI_EEPROM_MISO_pin PULLUP;
+#Net fpga_0_SPI_EEPROM_SS_pin<0> LOC=AG22;
+#Net fpga_0_SPI_EEPROM_SS_pin<0> TIG;
+#Net fpga_0_SPI_EEPROM_SS_pin<0> PULLUP;
+#
+##### Module LEDs_8Bit constraints
+#
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> LOC=AF19;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<0> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> LOC=AD5;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<1> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> LOC=AD6;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<2> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> LOC=AD7;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<3> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> LOC=AB8;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<4> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> LOC=AC7;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<5> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> LOC=AC9;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<6> TIG;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> LOC=AC10;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> IOSTANDARD = LVCMOS33;
+#Net fpga_0_LEDs_8Bit_GPIO_IO_pin<7> TIG;
+#
+##### Module LCD_OPTIONAL constraints
+#
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> LOC=AH19;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<0> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> LOC=AJ19;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<1> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> LOC=AK19;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<2> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> LOC=AG20;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<3> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> LOC=AH20;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<4> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> LOC=AJ20;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<5> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> LOC=AG21;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<6> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> LOC=AJ21;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<7> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> LOC=AK17;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<8> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> LOC=AH18;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<9> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> LOC=AK18;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<10> TIG;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> LOC=AJ17;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> IOSTANDARD = LVCMOS25;
+#Net fpga_0_LCD_OPTIONAL_GPIO_IO_pin<11> TIG;
+#
+##### Module pci_arbiter_0 constraints
+#
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> LOC=T4;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<1> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> LOC=T5;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<2> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> LOC=U8;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<3> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> LOC=V3;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<4> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> LOC=T6;
+#Net fpga_0_pci_arbiter_0_PCI_Gnt_n_pin<5> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> LOC=T3;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<1> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> LOC=R7;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<2> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> LOC=T8;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<3> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> LOC=T9;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<4> IOSTANDARD = PCI33_3;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> LOC=R9;
+#Net fpga_0_pci_arbiter_0_PCI_Req_n_pin<5> IOSTANDARD = PCI33_3;
+#
+##### Module PCI32_BRIDGE constraints
+#
+#Net fpga_0_PCI32_BRIDGE_PAR LOC=L8;
+#Net fpga_0_PCI32_BRIDGE_PAR IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_PAR BYPASS;
+#Net fpga_0_PCI32_BRIDGE_PERR_N LOC=M6;
+#Net fpga_0_PCI32_BRIDGE_PERR_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_PERR_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_SERR_N LOC=M7;
+#Net fpga_0_PCI32_BRIDGE_SERR_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_SERR_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_IRDY_N LOC=N5;
+#Net fpga_0_PCI32_BRIDGE_IRDY_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_IRDY_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_FRAME_N LOC=N8;
+#Net fpga_0_PCI32_BRIDGE_FRAME_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_FRAME_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_DEVSEL_N LOC=R3;
+#Net fpga_0_PCI32_BRIDGE_DEVSEL_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_DEVSEL_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_STOP_N LOC=P11;
+#Net fpga_0_PCI32_BRIDGE_STOP_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_STOP_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_TRDY_N LOC=M3;
+#Net fpga_0_PCI32_BRIDGE_TRDY_N IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_TRDY_N BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<31> LOC=P7;
+#Net fpga_0_PCI32_BRIDGE_AD<31> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<31> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<30> LOC=P6;
+#Net fpga_0_PCI32_BRIDGE_AD<30> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<30> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<29> LOC=K7;
+#Net fpga_0_PCI32_BRIDGE_AD<29> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<29> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<28> LOC=K6;
+#Net fpga_0_PCI32_BRIDGE_AD<28> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<28> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<27> LOC=L3;
+#Net fpga_0_PCI32_BRIDGE_AD<27> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<27> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<26> LOC=K8;
+#Net fpga_0_PCI32_BRIDGE_AD<26> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<26> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<25> LOC=M10;
+#Net fpga_0_PCI32_BRIDGE_AD<25> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<25> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<24> LOC=M8;
+#Net fpga_0_PCI32_BRIDGE_AD<24> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<24> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<23> LOC=J7;
+#Net fpga_0_PCI32_BRIDGE_AD<23> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<23> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<22> LOC=J6;
+#Net fpga_0_PCI32_BRIDGE_AD<22> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<22> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<21> LOC=K4;
+#Net fpga_0_PCI32_BRIDGE_AD<21> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<21> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<20> LOC=K3;
+#Net fpga_0_PCI32_BRIDGE_AD<20> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<20> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<19> LOC=N10;
+#Net fpga_0_PCI32_BRIDGE_AD<19> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<19> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<18> LOC=N9;
+#Net fpga_0_PCI32_BRIDGE_AD<18> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<18> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<17> LOC=H5;
+#Net fpga_0_PCI32_BRIDGE_AD<17> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<17> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<16> LOC=H4;
+#Net fpga_0_PCI32_BRIDGE_AD<16> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<16> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<15> LOC=J5;
+#Net fpga_0_PCI32_BRIDGE_AD<15> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<15> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<14> LOC=J4;
+#Net fpga_0_PCI32_BRIDGE_AD<14> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<14> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<13> LOC=L10;
+#Net fpga_0_PCI32_BRIDGE_AD<13> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<13> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<12> LOC=L9;
+#Net fpga_0_PCI32_BRIDGE_AD<12> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<12> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<11> LOC=G3;
+#Net fpga_0_PCI32_BRIDGE_AD<11> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<11> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<10> LOC=F5;
+#Net fpga_0_PCI32_BRIDGE_AD<10> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<10> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<9> LOC=F3;
+#Net fpga_0_PCI32_BRIDGE_AD<9> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<9> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<8> LOC=G5;
+#Net fpga_0_PCI32_BRIDGE_AD<8> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<8> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<7> LOC=N4;
+#Net fpga_0_PCI32_BRIDGE_AD<7> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<7> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<6> LOC=N3;
+#Net fpga_0_PCI32_BRIDGE_AD<6> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<6> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<5> LOC=E4;
+#Net fpga_0_PCI32_BRIDGE_AD<5> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<5> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<4> LOC=E3;
+#Net fpga_0_PCI32_BRIDGE_AD<4> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<4> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<3> LOC=F4;
+#Net fpga_0_PCI32_BRIDGE_AD<3> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<3> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<2> LOC=H3;
+#Net fpga_0_PCI32_BRIDGE_AD<2> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<2> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<1> LOC=L5;
+#Net fpga_0_PCI32_BRIDGE_AD<1> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<1> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_AD<0> LOC=L4;
+#Net fpga_0_PCI32_BRIDGE_AD<0> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_AD<0> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_CBE<3> LOC=R6;
+#Net fpga_0_PCI32_BRIDGE_CBE<3> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_CBE<3> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_CBE<2> LOC=R4;
+#Net fpga_0_PCI32_BRIDGE_CBE<2> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_CBE<2> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_CBE<1> LOC=L6;
+#Net fpga_0_PCI32_BRIDGE_CBE<1> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_CBE<1> BYPASS;
+#Net fpga_0_PCI32_BRIDGE_CBE<0> LOC=M5;
+#Net fpga_0_PCI32_BRIDGE_CBE<0> IOSTANDARD = PCI33_3;
+#Net fpga_0_PCI32_BRIDGE_CBE<0> BYPASS;
+#
+##### Module SysACE_CompactFlash constraints
+#
+#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin LOC=AF16;
+#Net fpga_0_SysACE_CompactFlash_SysACE_CLK_pin PERIOD = 29000 ps;
+#Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin LOC=AD4;
+#Net fpga_0_SysACE_CompactFlash_clk_enable_n_pin IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> LOC=AE6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<0> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> LOC=AE4;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<1> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> LOC=AE3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<2> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> LOC=AF6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<3> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> LOC=AF5;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<4> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> LOC=AF4;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<5> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> LOC=AF3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPA_pin<6> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> LOC=AG6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<0> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> LOC=AG5;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<1> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> LOC=AG3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<2> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> LOC=AH5;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<3> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> LOC=AH4;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<4> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> LOC=AH3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<5> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> LOC=AJ6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<6> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> LOC=AJ5;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<7> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> LOC=AJ4;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<8> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> LOC=AK6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<9> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> LOC=AK4;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<10> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> LOC=AK3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<11> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> LOC=AL6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<12> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> LOC=AL5;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<13> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> LOC=AL4;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<14> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> LOC=AA3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPD_pin<15> IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin LOC=AB6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_CEN_pin IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin LOC=AM5;
+#Net fpga_0_SysACE_CompactFlash_SysACE_OEN_pin IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin LOC=AB3;
+#Net fpga_0_SysACE_CompactFlash_SysACE_WEN_pin IOSTANDARD = LVCMOS33;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin LOC=AM6;
+#Net fpga_0_SysACE_CompactFlash_SysACE_MPIRQ_pin IOSTANDARD = LVCMOS33;
+#
+##### Module IIC_Bus constraints
+#
+#Net fpga_0_IIC_Bus_Scl_pin LOC=E7;
+#Net fpga_0_IIC_Bus_Scl_pin IOSTANDARD = LVCMOS33;
+#Net fpga_0_IIC_Bus_Sda_pin LOC=D7;
+#Net fpga_0_IIC_Bus_Sda_pin IOSTANDARD = LVCMOS33;
+#
+##### Module ORGate_1 constraints
+#
+#Net fpga_0_ORGate_1_Res_pin LOC=AE18;
+#Net fpga_0_ORGate_1_Res_pin TIG;
+#Net fpga_0_ORGate_1_Res_1_pin LOC=AE17;
+#Net fpga_0_ORGate_1_Res_1_pin TIG;
+#Net fpga_0_ORGate_1_Res_2_pin LOC=R11;
+#Net fpga_0_ORGate_1_Res_2_pin IOSTANDARD = PCI33_3;
+#
+##### Module TriMode_MAC_GMII constraints
+#
+#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin LOC = M12;
+#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin IOSTANDARD=LVCMOS33;
+#Net fpga_0_TriMode_MAC_GMII_PhyResetN_pin TIG;
+#
+##### Module Hard_Temac_0 constraints
+#
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> LOC = K9;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<3> SLEW=FAST;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> LOC = K11;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<2> SLEW=FAST;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> LOC = K12;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<1> SLEW=FAST;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> LOC = K13;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_TXD_0<0> SLEW=FAST;
+#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 LOC = L11;
+#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_TX_EN_0 SLEW=FAST;
+#Net fpga_0_Hard_Temac_0_MII_TX_ER_0 LOC = L14;
+#Net fpga_0_Hard_Temac_0_MII_TX_ER_0 IOSTANDARD=LVCMOS25;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> LOC = J9;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<3> IOBDELAY = NONE;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> LOC = J10;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<2> IOBDELAY = NONE;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> LOC = J11;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<1> IOBDELAY = NONE;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> LOC = J12;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_RXD_0<0> IOBDELAY = NONE;
+#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 LOC = H12;
+#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MII_RX_DV_0 IOBDELAY = NONE;
+#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 LOC = H18;
+#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOSTANDARD=LVCMOS25;
+#Net fpga_0_Hard_Temac_0_MII_RX_ER_0 IOBDELAY = NONE;
+#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 LOC=J14;
+#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 MAXSKEW= 2.0 ns;
+#Net fpga_0_Hard_Temac_0_MII_TX_CLK_0 IOSTANDARD=LVCMOS25;
+#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 LOC=K19;
+#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 MAXSKEW= 2.0 ns;
+#Net fpga_0_Hard_Temac_0_MII_RX_CLK_0 IOSTANDARD=LVCMOS25;
+#Net fpga_0_Hard_Temac_0_MDIO_0_pin LOC = L13;
+#Net fpga_0_Hard_Temac_0_MDIO_0_pin IOSTANDARD=LVCMOS33;
+#Net fpga_0_Hard_Temac_0_MDC_0_pin LOC = M13;
+#Net fpga_0_Hard_Temac_0_MDC_0_pin IOSTANDARD=LVCMOS33;
+#
+#Net fpga_0_DDR_CLK_FB TNM_NET = fpga_0_DDR_CLK_FB;
+#TIMESPEC TS_fpga_0_DDR_CLK_FB = PERIOD fpga_0_DDR_CLK_FB 10000 ps;
+#
+##### AR 22677
+#
+#AREA_GROUP "opb2plb" RANGE=SLICE_X20Y104:SLICE_X33Y139, SLICE_X34Y96:SLICE_X51Y139;
+#INST "opb2plb" AREA_GROUP = "opb2plb";
+#AREA_GROUP "pblock_spi_eeprom" RANGE=SLICE_X54Y92:SLICE_X67Y111;
+#INST "spi_eeprom" AREA_GROUP = "pblock_spi_eeprom";
+#AREA_GROUP "pblock_plb2opb" RANGE= SLICE_X34Y140:SLICE_X51Y191;
+#INST "plb2opb" AREA_GROUP = "pblock_plb2opb";
+## These two items here no longer exist in 8.2i
+## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CARRY_MUX*" AREA_GROUP = "pblock_plb2opb";
+## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/CYMUX_FIRST*" AREA_GROUP = "pblock_plb2opb";
+#
+## The path "I_PLB_ADDRPATH/I_PLBADDR_MUX" doesn't exist either; using *? to replace it
+## INST "plb/plb/I_PLB_ADDRPATH/I_PLBADDR_MUX/_n*" AREA_GROUP = "pblock_plb2opb";
+#INST "plb/plb/*?/_n*" AREA_GROUP = "pblock_plb2opb";
+#INST "plb/plb/I_PLB_ARBITER_LOGIC/I_MUXEDSIGNALS/*" AREA_GROUP = "pblock_plb2opb";
+#
+###################################
+#### Virtex-4 FX60-FF1152 MGT Null Tile LOCs ###
+###################################
+##MGT113A
+#INST MGT113AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y7;
+#NET "MGT113AB_TXN<1>" LOC = "A3"; #TXN
+#NET "MGT113AB_TXP<1>" LOC = "A4"; #TXP
+#NET "MGT113AB_RXN<1>" LOC = "A6"; #RXN
+#NET "MGT113AB_RXP<1>" LOC = "A7"; #RXP
+##MGT113B
+#INST MGT113AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y6;
+#NET "MGT113AB_TXN<0>" LOC = "D1"; #TXN
+#NET "MGT113AB_TXP<0>" LOC = "C1"; #TXP
+#NET "MGT113AB_RXN<0>" LOC = "G1"; #RXN
+#NET "MGT113AB_RXP<0>" LOC = "F1"; #RXP
+##MGT112A
+#INST MGT112AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y5;
+#NET "MGT112AB_TXN<1>" LOC = "T1"; #TXN
+#NET "MGT112AB_TXP<1>" LOC = "R1"; #TXP
+#NET "MGT112AB_RXN<1>" LOC = "N1"; #RXN
+#NET "MGT112AB_RXP<1>" LOC = "M1"; #RXP
+##MGT112B
+#INST MGT112AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y4;
+#NET "MGT112AB_TXN<0>" LOC = "V1"; #TXN
+#NET "MGT112AB_TXP<0>" LOC = "U1"; #TXP
+#NET "MGT112AB_RXN<0>" LOC = "AA1"; #RXN
+#NET "MGT112AB_RXP<0>" LOC = "Y1"; #RXP
+##MGT110A
+#INST MGT110AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y3;
+#NET "MGT110AB_TXN<1>" LOC = "AG1"; #TXN
+#NET "MGT110AB_TXP<1>" LOC = "AF1"; #TXP
+#NET "MGT110AB_RXN<1>" LOC = "AD1"; #RXN
+#NET "MGT110AB_RXP<1>" LOC = "AC1"; #RXP
+##MGT110B
+#INST MGT110AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y2;
+#NET "MGT110AB_TXN<0>" LOC = "AJ1"; #TXN
+#NET "MGT110AB_TXP<0>" LOC = "AH1"; #TXP
+#NET "MGT110AB_RXN<0>" LOC = "AM1"; #RXN
+#NET "MGT110AB_RXP<0>" LOC = "AL1"; #RXP
+##MGT109A
+#INST MGT109AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X1Y1;
+#NET "MGT109AB_TXN<1>" LOC = "AP10"; #TXN
+#NET "MGT109AB_TXP<1>" LOC = "AP9"; #TXP
+#NET "MGT109AB_RXN<1>" LOC = "AP7"; #RXN
+#NET "MGT109AB_RXP<1>" LOC = "AP6"; #RXP
+##MGT109B
+#INST MGT109AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X1Y0;
+#NET "MGT109AB_TXN<0>" LOC = "AP12"; #TXN
+#NET "MGT109AB_TXP<0>" LOC = "AP11"; #TXP
+#NET "MGT109AB_RXN<0>" LOC = "AP15"; #RXN
+#NET "MGT109AB_RXP<0>" LOC = "AP14"; #RXP
+##MGT102A
+#INST MGT102AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y7;
+#NET "MGT102AB_TXN<1>" LOC = "E34"; #TXN
+#NET "MGT102AB_TXP<1>" LOC = "D34"; #TXP
+#NET "MGT102AB_RXN<1>" LOC = "A32"; #RXN
+#NET "MGT102AB_RXP<1>" LOC = "A31"; #RXP
+#
+##MGT102B
+#INST MGT102AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y6;
+#NET "MGT102AB_TXN<0>" LOC = "G34"; #TXN
+#NET "MGT102AB_TXP<0>" LOC = "F34"; #TXP
+#NET "MGT102AB_RXN<0>" LOC = "K34"; #RXN
+#NET "MGT102AB_RXP<0>" LOC = "J34"; #RXP
+##MGT103A
+#INST MGT103AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y5;
+#NET "MGT103AB_TXN<1>" LOC = "W34"; #TXN
+#NET "MGT103AB_TXP<1>" LOC = "V34"; #TXP
+#NET "MGT103AB_RXN<1>" LOC = "T34"; #RXN
+#NET "MGT103AB_RXP<1>" LOC = "R34"; #RXP
+##MGT103B
+#INST MGT103AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y4;
+#NET "MGT103AB_TXN<0>" LOC = "AA34"; #TXN
+#NET "MGT103AB_TXP<0>" LOC = "Y34"; #TXP
+#NET "MGT103AB_RXN<0>" LOC = "AD34"; #RXN
+#NET "MGT103AB_RXP<0>" LOC = "AC34"; #RXP
+##MGT105A
+#INST MGT105AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y3;
+#NET "MGT105AB_TXN<1>" LOC = "AK34"; #TXN
+#NET "MGT105AB_TXP<1>" LOC = "AJ34"; #TXP
+#NET "MGT105AB_RXN<1>" LOC = "AG34"; #RXN
+#NET "MGT105AB_RXP<1>" LOC = "AF34"; #RXP
+##MGT105B
+#INST MGT105AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y2;
+#NET "MGT105AB_TXN<0>" LOC = "AM34"; #TXN
+#NET "MGT105AB_TXP<0>" LOC = "AL34"; #TXP
+#NET "MGT105AB_RXN<0>" LOC = "AP31"; #RXN
+#NET "MGT105AB_RXP<0>" LOC = "AP32"; #RXP
+##MGT106A
+#INST MGT106AB/*/GT11_INST_A/GT11_10GE_4_INST LOC=GT11_X0Y1;
+#NET "MGT106AB_TXN<1>" LOC = "AP22"; #TXN
+#NET "MGT106AB_TXP<1>" LOC = "AP23"; #TXP
+#NET "MGT106AB_RXN<1>" LOC = "AP25"; #RXN
+#NET "MGT106AB_RXP<1>" LOC = "AP26"; #RXP
+##MGT106B
+#INST MGT106AB/*/GT11_INST_B/GT11_10GE_4_INST LOC=GT11_X0Y0;
+#NET "MGT106AB_TXN<0>" LOC = "AP20"; #TXN
+#NET "MGT106AB_TXP<0>" LOC = "AP21"; #TXP
+#NET "MGT106AB_RXN<0>" LOC = "AP17"; #RXN
+#NET "MGT106AB_RXP<0>" LOC = "AP18"; #RXP
+#
projects / fleet.git / blobdiff