module main
- (sys_clk_pin, /* I think this is 100Mhz */
+ (sys_clk_pin, /* 100Mhz */
sys_rst_pin,
fpga_0_RS232_Uart_1_ctsN_pin,
fpga_0_RS232_Uart_1_rtsN_pin,
fpga_0_RS232_Uart_1_sin_pin,
- fpga_0_RS232_Uart_1_sout_pin
+ fpga_0_RS232_Uart_1_sout_pin,
+
+ fpga_0_DDR_SDRAM_DDR_Clk_pin,
+ fpga_0_DDR_SDRAM_DDR_Clk_n_pin,
+ fpga_0_DDR_SDRAM_DDR_Addr_pin,
+ fpga_0_DDR_SDRAM_DDR_BankAddr_pin,
+ fpga_0_DDR_SDRAM_DDR_CAS_n_pin,
+ fpga_0_DDR_SDRAM_DDR_CE_pin,
+ fpga_0_DDR_SDRAM_DDR_CS_n_pin,
+ fpga_0_DDR_SDRAM_DDR_RAS_n_pin,
+ fpga_0_DDR_SDRAM_DDR_WE_n_pin,
+ fpga_0_DDR_SDRAM_DDR_DM_pin,
+ fpga_0_DDR_SDRAM_DDR_DQS,
+ fpga_0_DDR_SDRAM_DDR_DQ,
+
+ vga_psave,
+ vga_hsync,
+ vga_vsync,
+ vga_sync,
+ vga_blank,
+ vga_r,
+ vga_g,
+ vga_b,
+ vga_clkout,
+
+ fpga_0_LEDs_8Bit_GPIO_IO_pin
);
input sys_clk_pin;
input fpga_0_RS232_Uart_1_sin_pin;
output fpga_0_RS232_Uart_1_sout_pin;
+ output fpga_0_DDR_SDRAM_DDR_Clk_pin;
+ output fpga_0_DDR_SDRAM_DDR_Clk_n_pin;
+ output [12:0] fpga_0_DDR_SDRAM_DDR_Addr_pin;
+ output [1:0] fpga_0_DDR_SDRAM_DDR_BankAddr_pin;
+ output fpga_0_DDR_SDRAM_DDR_CAS_n_pin;
+ output fpga_0_DDR_SDRAM_DDR_CE_pin;
+ output fpga_0_DDR_SDRAM_DDR_CS_n_pin;
+ output fpga_0_DDR_SDRAM_DDR_RAS_n_pin;
+ output fpga_0_DDR_SDRAM_DDR_WE_n_pin;
+ output [3:0] fpga_0_DDR_SDRAM_DDR_DM_pin;
+ inout [3:0] fpga_0_DDR_SDRAM_DDR_DQS;
+ inout [31:0] fpga_0_DDR_SDRAM_DDR_DQ;
+
+ wire [31:0] dram_addr;
+ wire dram_addr_r;
+ wire dram_addr_a;
+ wire dram_isread;
+ wire [63:0] dram_write_data;
+ wire dram_write_data_push;
+ wire dram_write_data_full;
+ wire [63:0] dram_read_data;
+ wire dram_read_data_pop;
+ wire dram_read_data_empty;
+ wire [1:0] dram_read_data_latency;
+
+ output vga_psave;
+ output vga_hsync;
+ output vga_vsync;
+ output vga_sync;
+ output vga_blank;
+ output [7:0] vga_r;
+ output [7:0] vga_g;
+ output [7:0] vga_b;
+ output vga_clkout;
+
wire clk;
- assign clk = sys_clk_pin;
+ wire clk_fb;
+ wire clk50mhz;
+ wire clk_unbuffered;
+
+ wire vga_clk;
+ wire vga_clk_fb;
+ wire vga_clk_unbuffered;
+
+ output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin;
+ wire [7:0] leds;
+ assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds;
+
+ assign leds[5:0] = dram_read_data[5:0];
+ assign leds[6] = dram_addr_r;
+ assign leds[7] = dram_addr_a;
+
+
+ //assign clk = sys_clk_pin;
+/*
+ reg clk_unbuffered;
+ initial clk_unbuffered = 0;
+
+ always @(posedge sys_clk_pin) begin
+ clk_unbuffered = ~clk_unbuffered;
+ end
+
+ assign clk_unbuffered = sys_clk_pin;
+*/
+ BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
+
+ DCM
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(8),
+ .CLKIN_PERIOD("10 ns")
+ ) mydcm(
+ .CLKIN (sys_clk_pin),
+ .CLKFB(clk_fb),
+ .CLKFX (clk_unbuffered),
+ .CLK0 (clk_fb)
+ );
+
+ BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
+ DCM // 25Mhz VGA clock
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(16),
+ .CLKIN_PERIOD("20 ns")
+ ) vgadcm (
+ .CLKIN (clk_unbuffered),
+ .CLKFB(vga_clk_fb),
+ .CLKFX (vga_clk_unbuffered),
+ .CLK0 (vga_clk_fb)
+ );
+
+
wire break_o;
wire break;
reg break_last;
wire sio_ce;
wire sio_ce_x4;
- //sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
- sasc_brg sasc_brg(clk, ser_rst, 8, 65, sio_ce, sio_ce_x4);
+ //sasc_brg sasc_brg(clk, ser_rst, 8, 65, sio_ce, sio_ce_x4);
+ // sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4);
+ sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
sasc_top sasc_top(clk, ser_rst,
fpga_0_RS232_Uart_1_sin_pin,
fpga_0_RS232_Uart_1_sout_pin,
*/
root my_root(clk, rst && !break_o,
root_in_r, root_in_a, root_in_d,
- root_out_r, root_out_a, root_out_d);
+ root_out_r, root_out_a, root_out_d,
+ dram_addr,
+ dram_addr_r,
+ dram_addr_a,
+ dram_isread,
+ dram_write_data,
+ dram_write_data_push,
+ dram_write_data_full,
+ dram_read_data,
+ dram_read_data_pop,
+ dram_read_data_empty,
+ dram_read_data_latency,
+ vga_clk,
+ vga_psave,
+ vga_hsync,
+ vga_vsync,
+ vga_sync,
+ vga_blank,
+ vga_r,
+ vga_g,
+ vga_b,
+ vga_clkout
+ );
/*
fifo4 my_root(clk, rst,
root_in_r, root_in_a, root_in_d,
data_to_fleet_read_enable_reg = 0;
data_to_host_write_enable_reg = 0;
end
-endmodule
+ ddr_ctrl
+ #(
+ .clk_freq( 50000000 ),
+ .clk_multiply( 12 ),
+ .clk_divide( 5 ),
+ .phase_shift( 0 ),
+ .wait200_init( 26 )
+ ) ddr_ctrl (
+ .ddr_a( fpga_0_DDR_SDRAM_DDR_Addr_pin ),
+ .ddr_clk( fpga_0_DDR_SDRAM_DDR_Clk_pin ),
+ .ddr_clk_n( fpga_0_DDR_SDRAM_DDR_Clk_n_pin ),
+ .ddr_ba( fpga_0_DDR_SDRAM_DDR_BankAddr_pin ),
+ .ddr_dq( fpga_0_DDR_SDRAM_DDR_DQ ),
+ .ddr_dm( fpga_0_DDR_SDRAM_DDR_DM_pin ),
+ .ddr_dqs( fpga_0_DDR_SDRAM_DDR_DQS ),
+ .ddr_cs_n( fpga_0_DDR_SDRAM_DDR_CS_n_pin ),
+ .ddr_ras_n( fpga_0_DDR_SDRAM_DDR_RAS_n_pin ),
+ .ddr_cas_n( fpga_0_DDR_SDRAM_DDR_CAS_n_pin ),
+ .ddr_we_n( fpga_0_DDR_SDRAM_DDR_WE_n_pin ),
+ .ddr_cke( fpga_0_DDR_SDRAM_DDR_CE_pin ),
+
+ .clk(clk),
+ .reset(!rst),
+ .rot(3'b011),
+
+ .fml_wr(!dram_isread && dram_addr_r),
+ .fml_done(dram_addr_a),
+ .fml_rd( dram_isread && dram_addr_r),
+ .fml_adr(dram_addr),
+ .fml_din(dram_write_data),
+ .fml_dout(dram_read_data),
+// .fml_msk(16'hffff)
+ .fml_msk(16'h0)
+ );
+endmodule
+
projects / fleet.git / blobdiff