cleanup to main.v

[fleet.git] / src / edu / berkeley / fleet / fpga / main.v

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index e70ddb5..921a40e 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -134,18 +134,6 @@ module main
   assign leds[6] = dram_addr_r;
   assign leds[7] = dram_addr_a;
 
-
-  //assign clk = sys_clk_pin;
-/*
-  reg clk_unbuffered;
-  initial clk_unbuffered = 0;
-
-  always @(posedge sys_clk_pin) begin
-    clk_unbuffered = ~clk_unbuffered;
-  end
-
-  assign clk_unbuffered = sys_clk_pin;
-*/
   BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
 
   DCM
@@ -201,8 +189,7 @@ module main
 
   wire sio_ce;
   wire sio_ce_x4;
-  //sasc_brg sasc_brg(clk, ser_rst, 8, 65, sio_ce, sio_ce_x4);
-  //  sasc_brg sasc_brg(clk, ser_rst, 3, 65, sio_ce, sio_ce_x4);
+
   sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
   sasc_top sasc_top(clk, ser_rst,
                     fpga_0_RS232_Uart_1_sin_pin,
@@ -370,69 +357,8 @@ module main
           .fml_adr(dram_addr),
           .fml_din(dram_write_data),
           .fml_dout(dram_read_data),
-//          .fml_msk(16'hffff)
           .fml_msk(16'h0)
    );
 
-/*
-   ddr2spa
-   #(
-//    fabtech : integer := virtex4;
-//    memtech : integer := 0;
-//    rskew   : integer := 0;
-//    hindex  : integer := 0;
-//    haddr   : integer := 0;
-//    hmask   : integer := 16#f00#;
-//    ioaddr  : integer := 16#000#;
-//    iomask  : integer := 16#fff#;
-    .mhz(100),
-    .clkmul(2),
-    .clkdiv(1),
-//    col     : integer := 9;
-//    Mbyte   : integer := 16;
-//    rstdel  : integer := 200;
-    .pwron(1),
-    //oepol   : integer := 0;
-    .ddrbits(64),
-    .ahbfreq(50),
-    //readdly : integer := 1; -- 1 added read latency cycle
-    //ddelayb0 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb1 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb2 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb3 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb4 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb5 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb6 : integer := 0; -- Data delay value (0 - 63)
-    //ddelayb7 : integer := 0; -- Data delay value (0 - 63)
-    //numidelctrl : integer := 4; 
-    .norefclk(1)
-    //odten    : integer := 0 
-   ) ddr2_spa (
-    .rst_ddr(sys_rst_pin),
-    .rst_ahb(rst),
-    .clk_ddr(sys_clk_pin),
-    .clk_ahb(clk),
-    //clkref200  : in  std_logic;
-    //lock       : out std_ulogic;    -- DCM locked
-    .clkddro(ddr2_clock),
-    .clkddri(ddr2_clock),
-    //ahbsi      : in  ahb_slv_in_type;
-    //ahbso      : out ahb_slv_out_type;
-    .ddr_clk(ddr2_Clk_pin),
-    .ddr_clkb(ddr2_Clk_n_pin),
-    .ddr_cke(ddr2_CE_pin),
-    .ddr_csb(ddr2_CS_n_pin),
-    .ddr_web(ddr2_WE_n_pin),
-    .ddr_rasb(ddr2_RAS_n_pin),
-    .ddr_casb(ddr2_CAS_n_pin),
-    .ddr_dm(ddr2_DM_pin),
-    .ddr_dqs(ddr2_DQS),
-    .ddr_dqsn(ddr2_DQS_n),
-    .ddr_ad(ddr2_Addr_pin),
-    .ddr_ba(ddr2_BankAddr_pin),
-    .ddr_dq(ddr2_DQ),
-    .ddr_odt(ddr2_ODT_pin)
-   );
-*/
 endmodule