module main
- (sys_clk_pin, /* I think this is 100Mhz */
+ (sys_clk_pin, /* 100Mhz */
sys_rst_pin,
fpga_0_RS232_Uart_1_ctsN_pin,
fpga_0_RS232_Uart_1_rtsN_pin,
fpga_0_RS232_Uart_1_sin_pin,
- fpga_0_RS232_Uart_1_sout_pin
+ fpga_0_RS232_Uart_1_sout_pin,
+
+ ddr1_Clk_pin,
+ ddr1_Clk_n_pin,
+ ddr1_Addr_pin,
+ ddr1_BankAddr_pin,
+ ddr1_CAS_n_pin,
+ ddr1_CE_pin,
+ ddr1_CS_n_pin,
+ ddr1_RAS_n_pin,
+ ddr1_WE_n_pin,
+ ddr1_DM_pin,
+ ddr1_DQS,
+ ddr1_DQ,
+
+ vga_psave,
+ vga_hsync,
+ vga_vsync,
+ vga_sync,
+ vga_blank,
+ vga_r,
+ vga_g,
+ vga_b,
+ vga_clkout,
+
+ fpga_0_LEDs_8Bit_GPIO_IO_pin
);
input sys_clk_pin;
input fpga_0_RS232_Uart_1_sin_pin;
output fpga_0_RS232_Uart_1_sout_pin;
+ output ddr1_Clk_pin;
+ output ddr1_Clk_n_pin;
+ output [12:0] ddr1_Addr_pin;
+ output [1:0] ddr1_BankAddr_pin;
+ output ddr1_CAS_n_pin;
+ output ddr1_CE_pin;
+ output ddr1_CS_n_pin;
+ output ddr1_RAS_n_pin;
+ output ddr1_WE_n_pin;
+ output [3:0] ddr1_DM_pin;
+ inout [3:0] ddr1_DQS;
+ inout [31:0] ddr1_DQ;
+
+ wire [31:0] dram_addr;
+ wire dram_addr_r;
+ wire dram_addr_a;
+ wire dram_isread;
+ wire [63:0] dram_write_data;
+ wire dram_write_data_push;
+ wire dram_write_data_full;
+ wire [63:0] dram_read_data;
+ wire dram_read_data_pop;
+ wire dram_read_data_empty;
+ wire [1:0] dram_read_data_latency;
+
+ output vga_psave;
+ output vga_hsync;
+ output vga_vsync;
+ output vga_sync;
+ output vga_blank;
+ output [7:0] vga_r;
+ output [7:0] vga_g;
+ output [7:0] vga_b;
+ output vga_clkout;
+
wire clk;
- assign clk = sys_clk_pin;
+ wire clk_fb;
+ wire clk50mhz;
+ wire clk_unbuffered;
+
+ wire vga_clk;
+ wire vga_clk_fb;
+ wire vga_clk_unbuffered;
+
+ output [7:0] fpga_0_LEDs_8Bit_GPIO_IO_pin;
+ wire [7:0] leds;
+ assign fpga_0_LEDs_8Bit_GPIO_IO_pin = ~leds;
+
+ assign leds[5:0] = dram_read_data[5:0];
+ assign leds[6] = dram_addr_r;
+ assign leds[7] = dram_addr_a;
+
+ BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));
+
+ DCM
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(8),
+ .CLKIN_PERIOD("10 ns")
+ ) mydcm(
+ .CLKIN (sys_clk_pin),
+ .CLKFB(clk_fb),
+ .CLKFX (clk_unbuffered),
+ .CLK0 (clk_fb)
+ );
+
+ BUFG GBUF_FOR_VGA_CLOCK (.I(vga_clk_unbuffered), .O(vga_clk));
+ DCM // 25Mhz VGA clock
+ #(
+ .CLKFX_MULTIPLY(4),
+ .CLKFX_DIVIDE(16),
+ .CLKIN_PERIOD("20 ns")
+ ) vgadcm (
+ .CLKIN (clk_unbuffered),
+ .CLKFB(vga_clk_fb),
+ .CLKFX (vga_clk_unbuffered),
+ .CLK0 (vga_clk_fb)
+ );
+
+
+ wire break_o;
wire break;
+ reg break_last;
+ reg send_k; initial send_k = 0;
wire rst;
assign rst = sys_rst_pin;
reg we;
reg re;
reg [7:0] data_to_host_r;
+ assign data_to_host = data_to_host_r;
wire ser_rst;
reg ser_rst_r;
initial ser_rst_r = 0;
- assign ser_rst = rst & ser_rst_r;
+ assign ser_rst = (rst & ser_rst_r);
wire sio_ce;
wire sio_ce_x4;
- sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
+
+ sasc_brg sasc_brg(sys_clk_pin, ser_rst, 8, 65, sio_ce, sio_ce_x4);
sasc_top sasc_top(clk, ser_rst,
fpga_0_RS232_Uart_1_sin_pin,
fpga_0_RS232_Uart_1_sout_pin,
data_to_host_write_enable,
data_to_host_full,
data_to_fleet_empty,
+ break_o,
break);
+ // break and break_o are _active high_
+ always @(posedge clk) break_last <= break_o;
+ assign break = break_o && !break_last;
+ assign break_done = !break_o && break_last;
+
reg data_to_host_write_enable_reg;
reg data_to_fleet_read_enable_reg;
wire root_out_a;
wire root_out_r;
wire [7:0] root_in_d;
+ wire [7:0] root_out_d;
-
- root my_root(clk, rst && !break,
- root_in_r, root_in_a, root_in_d,
- root_out_r, root_out_a, data_to_host);
-/*
- fifo4 my_root(clk, rst,
+ /*
+ * There is some very weird timing thing going on here; we need to
+ * hold reset low for more than one clock in order for it to propagate
+ * all the way to the docks.
+ */
+ root my_root(clk, rst && !break_o,
root_in_r, root_in_a, root_in_d,
- root_out_r, root_out_a, data_to_host);
-*/
+ root_out_r, root_out_a, root_out_d,
+ dram_addr,
+ dram_addr_r,
+ dram_addr_a,
+ dram_isread,
+ dram_write_data,
+ dram_write_data_push,
+ dram_write_data_full,
+ dram_read_data,
+ dram_read_data_pop,
+ dram_read_data_empty,
+ dram_read_data_latency,
+ vga_clk,
+ vga_psave,
+ vga_hsync,
+ vga_vsync,
+ vga_sync,
+ vga_blank,
+ vga_r,
+ vga_g,
+ vga_b,
+ vga_clkout
+ );
+
assign root_out_a = root_out_a_reg;
assign root_in_r = root_in_r_reg;
assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
// fpga -> host
always @(posedge clk)
begin
- data_to_host_write_enable_reg = 0;
- if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
- data_to_host_write_enable_reg = 1;
+ if (break) begin
+ root_out_a_reg = 0;
+ data_to_host_write_enable_reg <= 0;
+
+ end else if (break_done) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= 111;
+ send_k <= 1;
+ end else if (send_k) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= 107;
+ send_k <= 0;
+
+
+ end else if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= root_out_d;
root_out_a_reg = 1;
end else if (root_out_a_reg && !root_out_r) begin
+ data_to_host_write_enable_reg <= 0;
root_out_a_reg = 0;
+ end else begin
+ data_to_host_write_enable_reg <= 0;
end
end
always @(posedge clk)
begin
ser_rst_r <= 1;
- data_to_fleet_read_enable_reg = 0;
+ if (break) begin
+ root_in_r_reg <= 0;
+ root_in_d_reg <= 0;
+ data_to_fleet_read_enable_reg <= 0;
+ end else
+
if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
- root_in_r_reg = 1;
- root_in_d_reg = data_to_fleet;
- data_to_fleet_read_enable_reg = 1;
+ root_in_r_reg <= 1;
+ root_in_d_reg <= data_to_fleet;
+ data_to_fleet_read_enable_reg <= 1;
end else begin
+ data_to_fleet_read_enable_reg <= 0;
if (root_in_a) begin
- root_in_r_reg = 0;
+ root_in_r_reg <= 0;
end
end
end
data_to_fleet_read_enable_reg = 0;
data_to_host_write_enable_reg = 0;
end
-endmodule
+ ddr_ctrl
+ #(
+ .clk_freq( 50000000 ),
+ .clk_multiply( 12 ),
+ .clk_divide( 5 ),
+ .phase_shift( 0 ),
+ .wait200_init( 26 )
+ ) ddr_ctrl (
+ .ddr_a( ddr1_Addr_pin ),
+ .ddr_clk( ddr1_Clk_pin ),
+ .ddr_clk_n( ddr1_Clk_n_pin ),
+ .ddr_ba( ddr1_BankAddr_pin ),
+ .ddr_dq( ddr1_DQ ),
+ .ddr_dm( ddr1_DM_pin ),
+ .ddr_dqs( ddr1_DQS ),
+ .ddr_cs_n( ddr1_CS_n_pin ),
+ .ddr_ras_n( ddr1_RAS_n_pin ),
+ .ddr_cas_n( ddr1_CAS_n_pin ),
+ .ddr_we_n( ddr1_WE_n_pin ),
+ .ddr_cke( ddr1_CE_pin ),
+
+ .clk(clk),
+ .reset(!rst),
+ .rot(3'b100),
+
+ .fml_wr(!dram_isread && dram_addr_r),
+ .fml_done(dram_addr_a),
+ .fml_rd( dram_isread && dram_addr_r),
+ .fml_adr(dram_addr),
+ .fml_din(dram_write_data),
+ .fml_dout(dram_read_data),
+ .fml_msk(16'h0)
+ );
+endmodule
+
projects / fleet.git / blobdiff