-//----------------------------------------------------------------------------
-// user_fifo_test.v
-//----------------------------------------------------------------------------
-
-`timescale 1ps / 1ps
module main
- (
- // User clock ports
- Clkin_p,
- Clkin_m,
-
- // SelectMAP interface ports
- D, // Data bus
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK, // Local CCLK output
- gpleds
- );
-
- // User clock/reset ports
- input Clkin_p;
- input Clkin_m;
-
- // SelectMAP protocol ports
- inout [0:7] D;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
- output [6:1] gpleds;
-
-
- // Wires
- wire CCLK_int;
-
- wire [0:31] LoopData;
- wire [0:31] LoopDataW;
- wire LoopEmpty;
- wire LoopFull;
-
- wire [0:7] D_I;
- wire [0:7] D_O;
- wire [0:7] D_T;
-
- wire User_Clk;
- wire User_Rst;
-
- reg [6:1] gpleds_reg;
-
- // synthesis attribute tig of activate_r is yes;
- wire activate_r;
- // synthesis attribute tig of activate_a is yes;
- wire activate_a;
-
- wire [7:0] write_data;
- wire write_enable;
- wire write_full;
-
- wire [7:0] read_data;
- wire read_empty;
- wire [7:0] read_wire;
-
- reg [7:0] write_reg;
- reg [7:0] read_reg;
-
- reg [7:0] read_in;
- wire read_enable;
- reg read_enable_reg;
- reg write_enable_reg;
+ (sys_clk_pin, /* I think this is 100Mhz */
+ sys_rst_pin,
+ fpga_0_RS232_Uart_1_ctsN_pin,
+ fpga_0_RS232_Uart_1_rtsN_pin,
+ fpga_0_RS232_Uart_1_sin_pin,
+ fpga_0_RS232_Uart_1_sout_pin
+ );
+
+ input sys_clk_pin;
+ input sys_rst_pin;
+ input fpga_0_RS232_Uart_1_ctsN_pin;
+ output fpga_0_RS232_Uart_1_rtsN_pin;
+ input fpga_0_RS232_Uart_1_sin_pin;
+ output fpga_0_RS232_Uart_1_sout_pin;
+
+ wire clk;
+ assign clk = sys_clk_pin;
+ wire break;
+ wire rst;
+ assign rst = sys_rst_pin;
+
+ wire data_to_host_full;
+ wire data_to_host_write_enable;
+ wire [7:0] data_to_host;
+
+ wire data_to_fleet_empty;
+ wire data_to_fleet_read_enable;
+ wire [7:0] data_to_fleet;
+
+ reg we;
+ reg re;
+ reg [7:0] data_to_host_r;
+
+ wire ser_rst;
+ reg ser_rst_r;
+ initial ser_rst_r = 0;
+ assign ser_rst = rst & ser_rst_r;
+
+ wire sio_ce;
+ wire sio_ce_x4;
+ sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
+ sasc_top sasc_top(clk, ser_rst,
+ fpga_0_RS232_Uart_1_sin_pin,
+ fpga_0_RS232_Uart_1_sout_pin,
+ fpga_0_RS232_Uart_1_ctsN_pin,
+ fpga_0_RS232_Uart_1_rtsN_pin,
+ sio_ce,
+ sio_ce_x4,
+ data_to_host,
+ data_to_fleet,
+ data_to_fleet_read_enable,
+ data_to_host_write_enable,
+ data_to_host_full,
+ data_to_fleet_empty,
+ break);
+
+ reg data_to_host_write_enable_reg;
+ reg data_to_fleet_read_enable_reg;
reg root_out_a_reg;
reg root_in_r_reg;
wire root_out_r;
wire [7:0] root_in_d;
- root my_root(User_Clk, root_in_r, root_in_a, root_in_d,
- root_out_r, root_out_a, write_data);
- assign root_out_a = root_out_a_reg;
- assign root_in_r = root_in_r_reg;
- assign read_enable = read_enable_reg;
- assign write_enable = write_enable_reg;
- assign root_in_d = root_in_d_reg;
+ root my_root(clk, rst && !break,
+ root_in_r, root_in_a, root_in_d,
+ root_out_r, root_out_a, data_to_host);
+/*
+ fifo4 my_root(clk, rst,
+ root_in_r, root_in_a, root_in_d,
+ root_out_r, root_out_a, data_to_host);
+*/
+ assign root_out_a = root_out_a_reg;
+ assign root_in_r = root_in_r_reg;
+ assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
+ assign data_to_host_write_enable = data_to_host_write_enable_reg;
+ assign root_in_d = root_in_d_reg;
// fpga -> host
- always @(posedge User_Clk)
+ always @(posedge clk)
begin
- write_enable_reg = 0;
- if (root_out_r && !root_out_a_reg && !write_full) begin
- write_enable_reg = 1;
+ data_to_host_write_enable_reg = 0;
+ if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
+ data_to_host_write_enable_reg = 1;
root_out_a_reg = 1;
end else if (root_out_a_reg && !root_out_r) begin
root_out_a_reg = 0;
end
- gpleds_reg[4] = write_enable_reg;
- gpleds_reg[5] = root_out_r;
- gpleds_reg[6] = root_out_a_reg;
end
// host -> fpga
- always @(posedge User_Clk)
+ always @(posedge clk)
begin
- read_enable_reg = 0;
- if (!read_empty && !root_in_r_reg && !root_in_a) begin
+ ser_rst_r <= 1;
+ data_to_fleet_read_enable_reg = 0;
+ if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
root_in_r_reg = 1;
- root_in_d_reg = read_data;
- read_enable_reg = 1;
+ root_in_d_reg = data_to_fleet;
+ data_to_fleet_read_enable_reg = 1;
end else begin
if (root_in_a) begin
root_in_r_reg = 0;
end
end
- gpleds_reg[1] = read_enable_reg;
- gpleds_reg[2] = root_in_r_reg;
- gpleds_reg[3] = root_in_a;
end
- assign gpleds = gpleds_reg;
-
initial
begin
- gpleds_reg = 0;
root_in_r_reg = 0;
root_in_d_reg = 0;
root_out_a_reg = 0;
- root_in_r_reg = 0;
- read_enable_reg = 0;
- read_reg = 0;
- read_in = 255;
+ data_to_fleet_read_enable_reg = 0;
+ data_to_host_write_enable_reg = 0;
end
-
- // IO buffers
- OBUF obuf_cclk( .I( CCLK_int ),
- .O( CCLK )
- );
-
- IOBUF iobuf_d0( .I( D_O[0] ),
- .IO( D[0] ),
- .O( D_I[0] ),
- .T( D_T[0] )
- );
-
- IOBUF iobuf_d1( .I( D_O[1] ),
- .IO( D[1] ),
- .O( D_I[1] ),
- .T( D_T[1] )
- );
-
- IOBUF iobuf_d2( .I( D_O[2] ),
- .IO( D[2] ),
- .O( D_I[2] ),
- .T( D_T[2] )
- );
-
- IOBUF iobuf_d3( .I( D_O[3] ),
- .IO( D[3] ),
- .O( D_I[3] ),
- .T( D_T[3] )
- );
-
- IOBUF iobuf_d4( .I( D_O[4] ),
- .IO( D[4] ),
- .O( D_I[4] ),
- .T( D_T[4] )
- );
-
- IOBUF iobuf_d5( .I( D_O[5] ),
- .IO( D[5] ),
- .O( D_I[5] ),
- .T( D_T[5] )
- );
-
- IOBUF iobuf_d6( .I( D_O[6] ),
- .IO( D[6] ),
- .O( D_I[6] ),
- .T( D_T[6] )
- );
-
- IOBUF iobuf_d7( .I( D_O[7] ),
- .IO( D[7] ),
- .O( D_I[7] ),
- .T( D_T[7] )
- );
-
- // Clock buffer and reset
- IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
- .IB( Clkin_m ),
- .O( User_Clk )
- );
-
- wire [0:3] rst;
-
- FD rst0( .D( 1'b0 ),
- .Q( rst[0] ),
- .C( User_Clk )
- );
- defparam rst0.INIT = 1'b1;
-
- FD rst1( .D( rst[0] ),
- .Q( rst[1] ),
- .C( User_Clk )
- );
- defparam rst1.INIT = 1'b1;
-
- FD rst2( .D( rst[1] ),
- .Q( rst[2] ),
- .C( User_Clk )
- );
- defparam rst2.INIT = 1'b1;
-
- FD rst3( .D( rst[2] ),
- .Q( rst[3] ),
- .C( User_Clk )
- );
- defparam rst3.INIT = 1'b1;
-
- assign User_Rst = |rst;
-
-
- // FIFO module instantiation
- user_fifo test_fifo(
- .WrFifo_Din( write_data ),
- .WrFifo_WrEn( write_enable ),
- .WrFifo_Full( write_full ),
- .WrFifo_WrCnt( ),
- .RdFifo_Dout( read_data ),
- .RdFifo_RdEn( read_enable ),
- .RdFifo_Empty( read_empty ),
- .RdFifo_RdCnt( ),
- .User_Rst( User_Rst ),
- .User_Clk( User_Clk ),
- .Sys_Rst( User_Rst ),
- .Sys_Clk( User_Clk ),
- .D_I( D_I ),
- .D_O( D_O ),
- .D_T( D_T ),
- .RDWR_B( RDWR_B ),
- .CS_B( CS_B ),
- .INIT_B( INIT_B ),
- .CCLK( CCLK_int )
- );
-
endmodule
+
+
projects / fleet.git / blobdiff