checkpoint

[fleet.git] / src / edu / berkeley / fleet / fpga / main.v

diff --git a/src/edu/berkeley/fleet/fpga/main.v b/src/edu/berkeley/fleet/fpga/main.v
index 505d6a7..9c6fcb8 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/main.v
+++ b/src/edu/berkeley/fleet/fpga/main.v
@@ -17,6 +17,7 @@ module main
 
   wire clk;
   assign clk = sys_clk_pin;
+  wire break;
   wire rst;
   assign rst = sys_rst_pin;
 
@@ -32,31 +33,6 @@ module main
   reg re;
   reg [7:0] data_to_host_r;
 
-/*
-  assign data_to_host              = data_to_host_r;
-  assign data_to_host_write_enable = we;
-  assign data_to_fleet_read_enable = re;
-
-  reg [7:0] count;
-  initial count = 0;
-  initial we = 0;
-  initial re = 0;
-  initial data_to_host_r = 107;
-  always @(posedge clk) begin
-    if (re && !data_to_fleet_empty) begin
-      data_to_host_r <= data_to_fleet;
-      we <= 1;
-    end else begin
-      we <= 0;
-    end
-    if (data_to_host_full || data_to_fleet_empty) begin
-      re <= 0;
-    end else begin
-      re <= 1;
-    end
-  end
-*/
-
   wire ser_rst;
   reg ser_rst_r;
   initial ser_rst_r = 0;
@@ -77,7 +53,8 @@ module main
                     data_to_fleet_read_enable,
                     data_to_host_write_enable,
                     data_to_host_full,
-                    data_to_fleet_empty);
+                    data_to_fleet_empty,
+                    break);
 
    reg data_to_host_write_enable_reg;
    reg data_to_fleet_read_enable_reg;
@@ -91,11 +68,12 @@ module main
    wire root_out_r;
    wire [7:0] root_in_d;
 
-   root my_root(clk, rst, 
+
+   root my_root(clk, rst && !break, 
                 root_in_r,  root_in_a,  root_in_d,
                 root_out_r, root_out_a, data_to_host);
 /*
-   fifo4 my_root(clk,
+   fifo4 my_root(clk, rst,
                 root_in_r,  root_in_a,  root_in_d,
                 root_out_r, root_out_a, data_to_host);
 */
@@ -117,39 +95,24 @@ module main
      end
    end
 
-   // awful hack to flush the superfluous null byte that seems to appear on bootup
-   reg [15:0] boot_counter;
-
    // host -> fpga
    always @(posedge clk)
    begin
      ser_rst_r <= 1;
-/*
-     if (boot_counter != 500) begin
-       data_to_fleet_read_enable_reg = 1;
-       if (sio_ce) begin
-         boot_counter <= boot_counter + 1;
-       end
+     data_to_fleet_read_enable_reg = 0;
+     if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
+        root_in_r_reg = 1;
+        root_in_d_reg = data_to_fleet;
+        data_to_fleet_read_enable_reg = 1;
      end else begin
-*/
-       data_to_fleet_read_enable_reg = 0;
-       if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
-          root_in_r_reg = 1;
-          root_in_d_reg = data_to_fleet;
-          data_to_fleet_read_enable_reg = 1;
-       end else begin
-          if (root_in_a) begin
-            root_in_r_reg = 0;
-          end
-       end
-/*
+        if (root_in_a) begin
+          root_in_r_reg = 0;
+        end
      end
-*/
    end
 
    initial
    begin
-     boot_counter = 0;
      root_in_r_reg = 0;
      root_in_d_reg = 0;
      root_out_a_reg = 0;