-`timescale 1ps / 1ps
-
-// Copyright (c) 2005-2006, Regents of the University of California
-// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without modification,
-// are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer
-// in the documentation and/or other materials provided with the
-// distribution.
-// - Neither the name of the University of California, Berkeley nor the
-// names of its contributors may be used to endorse or promote
-// products derived from this software without specific prior
-// written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
-// ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-// ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-//----------------------------------------------------------------------------
-// user_fifo.v
-//----------------------------------------------------------------------------
-
-`timescale 1ps / 1ps
-
-module user_fifo
- (
- // FIFO interface ports
- WrFifo_Din, // Write FIFO data-in
- WrFifo_WrEn, // Write FIFO write enable
- WrFifo_Full, // Write FIFO full
- WrFifo_WrCnt, // Write FIFO write count
- RdFifo_Dout, // Read FIFO data-out
- RdFifo_RdEn, // Read FIFO read enable
- RdFifo_Empty, // Read FIFO empty
- RdFifo_RdCnt, // Read FIFO read count
- User_Rst, // User reset
- User_Clk, // User clock
- Sys_Rst, // System clock reset
- Sys_Clk, // 100MHz system clock for CCLK generation
-
- // SelectMAP interface ports
- D_I, // Data bus input
- D_O, // Data bus output
- D_T, // Data bus tristate enable
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK // CCLK output
- );
-
- // FIFO interface ports
- input [0:7] WrFifo_Din;
- input WrFifo_WrEn;
- output WrFifo_Full;
- output [0:7] WrFifo_WrCnt;
- output [0:7] RdFifo_Dout;
- input RdFifo_RdEn;
- output RdFifo_Empty;
- output [0:7] RdFifo_RdCnt;
- input User_Rst;
- input User_Clk;
- input Sys_Rst;
- input Sys_Clk;
-
- // SelectMAP protocol ports
- input [0:7] D_I;
- output [0:7] D_O;
- output [0:7] D_T;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
-
- // ____ __ _ _ _ _ //
- // | _ \ ___ / _(_)_ __ (_) |_(_) ___ _ __ ___ //
- // | | | |/ _ \ |_| | '_ \| | __| |/ _ \| '_ \/ __| //
- // | |_| | __/ _| | | | | | |_| | (_) | | | \__ \ //
- // |____/ \___|_| |_|_| |_|_|\__|_|\___/|_| |_|___/ //
- // //
-
- //----------------------------------------------------------------------------
- // Signal definitions
- //----------------------------------------------------------------------------
- // Write FIFO signals
- wire [0:7] WrFifo_Dout;
- wire WrFifo_Empty;
- wire WrFifo_RdEn;
- wire [0:7] WrFifo_RdCnt;
- wire [0:7] WrFifo_RdCnt_int;
- wire [0:7] WrFifo_WrCnt_int;
-
- // Read FIFO signals
- wire [0:7] RdFifo_Din;
- wire RdFifo_Full;
- wire RdFifo_WrEn;
- wire [0:7] RdFifo_WrCnt;
- wire [0:7] RdFifo_WrCnt_int;
- wire [0:7] RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // IO Registers
- //----------------------------------------------------------------------------
- reg CCLK;
-
- reg [0:7] D_I_reg; // synthesis attribute iob of D_I_reg is true;
- reg [0:7] D_O_reg; // synthesis attribute iob of D_O_reg is true;
- reg RDWR_B_reg; // synthesis attribute iob of RDWR_B_reg is true;
- reg CS_B_reg; // synthesis attribute iob of CS_B_reg is true;
- reg INIT_B_reg; // synthesis attribute iob of INIT_B_reg is true;
-
- // Outputs
- assign D_O = D_O_reg;
- assign INIT_B = INIT_B_reg;
-
- // Inputs
- always @( posedge Sys_Clk )
- begin
- D_I_reg <= D_I;
- RDWR_B_reg <= RDWR_B;
- CS_B_reg <= CS_B;
- end
-
- //----------------------------------------------------------------------------
- // Generate CCLK and associated reset
- //----------------------------------------------------------------------------
- reg SYNC_done;
- reg SYNC_done_dly;
- reg CS_B_reg_dly;
-
- always @( posedge Sys_Clk )
- begin
- CS_B_reg_dly <= CS_B_reg;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done <= 1'b0;
- else if (RDWR_B_reg && ~CS_B_reg)
- SYNC_done <= 1'b1;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- SYNC_done_dly <= 1'b0;
- else
- SYNC_done_dly <= SYNC_done;
- end
-
- always @( posedge Sys_Clk )
- begin
- if (Sys_Rst)
- CCLK <= 1'b0;
- else if (~CS_B_reg && CS_B_reg_dly && CCLK)
- CCLK <= 1'b1;
- else
- CCLK <= ~CCLK;
- end
-
- // _____ ___ _____ ___ //
- // | ___|_ _| ___/ _ \ ___ //
- // | |_ | || |_ | | | / __| //
- // | _| | || _|| |_| \__ \ //
- // |_| |___|_| \___/|___/ //
- // //
- // Write FIFO: The write is with respect to the user. The user writes data to this
- // FIFO and the control side of SelectMAP reads the data.
- //
- // Read FIFO: The read is with respect to the user. The user reads data sent from the
- // control side of SelectMAP.
- //
-
- //----------------------------------------------------------------------------
- // Read FIFO
- //----------------------------------------------------------------------------
- assign RdFifo_WrEn = SYNC_done_dly && ~RDWR_B_reg && ~CS_B_reg && ~RdFifo_Full && CCLK;
- assign RdFifo_Din = D_I_reg;
-
- async_fifo_8_8_128 RdFifo( .din( RdFifo_Din ),
- .dout( RdFifo_Dout ),
- .rd_clk( User_Clk ),
- .rd_en( RdFifo_RdEn ),
- .wr_clk( Sys_Clk ),
- .wr_en( RdFifo_WrEn ),
- .rst( User_Rst ),
- .empty( RdFifo_Empty ),
- .full( RdFifo_Full ),
- .rd_data_count( RdFifo_RdCnt_int ),
- .wr_data_count( RdFifo_WrCnt_int ) );
-
- assign RdFifo_WrCnt = 8'd129 - RdFifo_WrCnt_int;
- assign RdFifo_RdCnt = RdFifo_RdCnt_int;
-
- //----------------------------------------------------------------------------
- // Write FIFO
- //----------------------------------------------------------------------------
- assign WrFifo_RdEn = SYNC_done_dly && RDWR_B_reg && ~CS_B_reg && ~WrFifo_Empty && CCLK;
-
- async_fifo_8_8_128 WrFifo( .din( WrFifo_Din ),
- .dout( WrFifo_Dout ),
- .rd_clk( Sys_Clk ),
- .rd_en( WrFifo_RdEn ),
- .wr_clk( User_Clk ),
- .wr_en( WrFifo_WrEn ),
- .rst( User_Rst ),
- .empty( WrFifo_Empty ),
- .full( WrFifo_Full ),
- .rd_data_count( WrFifo_RdCnt_int ),
- .wr_data_count( WrFifo_WrCnt_int ) );
-
- assign WrFifo_WrCnt = 8'd129 - WrFifo_WrCnt_int;
- assign WrFifo_RdCnt = WrFifo_RdCnt_int;
-
- // ____ _ _ __ __ _ ____ //
- // / ___| ___| | ___ ___| |_| \/ | / \ | _ \ //
- // \___ \ / _ \ |/ _ \/ __| __| |\/| | / _ \ | |_) | //
- // ___) | __/ | __/ (__| |_| | | |/ ___ \| __/ //
- // |____/ \___|_|\___|\___|\__|_| |_/_/ \_\_| //
- // //
-
- //----------------------------------------------------------------------------
- // SelectMAP control outputs
- //----------------------------------------------------------------------------
- wire [0:7] DataCnt = RDWR_B_reg ? WrFifo_RdCnt : RdFifo_WrCnt;
-
- assign D_T = {8{(~RDWR_B & ~CS_B)}}; // stop driving if master is sending
-
- always @( posedge Sys_Clk )
- begin
- D_O_reg <= CS_B_reg ? DataCnt : WrFifo_Dout;
- INIT_B_reg <= WrFifo_Empty;
- end
-
- //----------------------------------------------------------------------------
-
-endmodule
-
module main
- (
- // User clock ports
- Clkin_p,
- Clkin_m,
-
- // SelectMAP interface ports
- D, // Data bus
- RDWR_B, // Read/write signal
- CS_B, // Chip select
- INIT_B, // Initialization/interrupt signal
- CCLK, // Local CCLK output
- gpleds
- );
-
- // User clock/reset ports
- input Clkin_p;
- input Clkin_m;
-
- // SelectMAP protocol ports
- inout [0:7] D;
- input RDWR_B;
- input CS_B;
- output INIT_B;
- output CCLK;
- output [6:1] gpleds;
-
-
- // Wires
- wire CCLK_int;
-
- wire [0:31] LoopData;
- wire [0:31] LoopDataW;
- wire LoopEmpty;
- wire LoopFull;
-
- wire [0:7] D_I;
- wire [0:7] D_O;
- wire [0:7] D_T;
-
- wire User_Clk;
- wire User_Rst;
-
- reg [6:1] gpleds_reg;
-
- // synthesis attribute tig of activate_r is yes;
- wire activate_r;
- // synthesis attribute tig of activate_a is yes;
- wire activate_a;
-
- wire [7:0] write_data;
- wire write_enable;
- wire write_full;
-
- wire [7:0] read_data;
- wire read_empty;
- wire [7:0] read_wire;
-
- reg [7:0] write_reg;
- reg [7:0] read_reg;
-
- reg [7:0] read_in;
- wire read_enable;
- reg read_enable_reg;
- reg write_enable_reg;
+ (sys_clk_pin, /* I think this is 100Mhz */
+ sys_rst_pin,
+ fpga_0_RS232_Uart_1_ctsN_pin,
+ fpga_0_RS232_Uart_1_rtsN_pin,
+ fpga_0_RS232_Uart_1_sin_pin,
+ fpga_0_RS232_Uart_1_sout_pin
+ );
+
+ input sys_clk_pin;
+ input sys_rst_pin;
+ input fpga_0_RS232_Uart_1_ctsN_pin;
+ output fpga_0_RS232_Uart_1_rtsN_pin;
+ input fpga_0_RS232_Uart_1_sin_pin;
+ output fpga_0_RS232_Uart_1_sout_pin;
+
+ wire clk;
+ assign clk = sys_clk_pin;
+ wire break;
+ wire rst;
+ assign rst = sys_rst_pin;
+
+ wire data_to_host_full;
+ wire data_to_host_write_enable;
+ wire [7:0] data_to_host;
+
+ wire data_to_fleet_empty;
+ wire data_to_fleet_read_enable;
+ wire [7:0] data_to_fleet;
+
+ reg we;
+ reg re;
+ reg [7:0] data_to_host_r;
+
+ wire ser_rst;
+ reg ser_rst_r;
+ initial ser_rst_r = 0;
+ assign ser_rst = rst & ser_rst_r;
+
+ wire sio_ce;
+ wire sio_ce_x4;
+ sasc_brg sasc_brg(clk, ser_rst, 10, 217, sio_ce, sio_ce_x4);
+ sasc_top sasc_top(clk, ser_rst,
+ fpga_0_RS232_Uart_1_sin_pin,
+ fpga_0_RS232_Uart_1_sout_pin,
+ fpga_0_RS232_Uart_1_ctsN_pin,
+ fpga_0_RS232_Uart_1_rtsN_pin,
+ sio_ce,
+ sio_ce_x4,
+ data_to_host,
+ data_to_fleet,
+ data_to_fleet_read_enable,
+ data_to_host_write_enable,
+ data_to_host_full,
+ data_to_fleet_empty,
+ break);
+
+ reg data_to_host_write_enable_reg;
+ reg data_to_fleet_read_enable_reg;
reg root_out_a_reg;
reg root_in_r_reg;
wire root_out_r;
wire [7:0] root_in_d;
- root my_root(User_Clk, root_in_r, root_in_a, root_in_d,
- root_out_r, root_out_a, write_data);
- assign root_out_a = root_out_a_reg;
- assign root_in_r = root_in_r_reg;
- assign read_enable = read_enable_reg;
- assign write_enable = write_enable_reg;
- assign root_in_d = root_in_d_reg;
+ root my_root(clk, rst && !break,
+ root_in_r, root_in_a, root_in_d,
+ root_out_r, root_out_a, data_to_host);
+/*
+ fifo4 my_root(clk, rst,
+ root_in_r, root_in_a, root_in_d,
+ root_out_r, root_out_a, data_to_host);
+*/
+ assign root_out_a = root_out_a_reg;
+ assign root_in_r = root_in_r_reg;
+ assign data_to_fleet_read_enable = data_to_fleet_read_enable_reg;
+ assign data_to_host_write_enable = data_to_host_write_enable_reg;
+ assign root_in_d = root_in_d_reg;
// fpga -> host
- always @(posedge User_Clk)
+ always @(posedge clk)
begin
- write_enable_reg = 0;
- if (root_out_r && !root_out_a_reg && !write_full) begin
- write_enable_reg = 1;
+ data_to_host_write_enable_reg = 0;
+ if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
+ data_to_host_write_enable_reg = 1;
root_out_a_reg = 1;
end else if (root_out_a_reg && !root_out_r) begin
root_out_a_reg = 0;
end
- gpleds_reg[4] = write_enable_reg;
- gpleds_reg[5] = root_out_r;
- gpleds_reg[6] = root_out_a_reg;
end
// host -> fpga
- always @(posedge User_Clk)
+ always @(posedge clk)
begin
- read_enable_reg = 0;
- if (!read_empty && !root_in_r_reg && !root_in_a) begin
+ ser_rst_r <= 1;
+ data_to_fleet_read_enable_reg = 0;
+ if (!data_to_fleet_empty && !root_in_r_reg && !root_in_a) begin
root_in_r_reg = 1;
- root_in_d_reg = read_data;
- read_enable_reg = 1;
+ root_in_d_reg = data_to_fleet;
+ data_to_fleet_read_enable_reg = 1;
end else begin
if (root_in_a) begin
root_in_r_reg = 0;
end
end
- gpleds_reg[1] = read_enable_reg;
- gpleds_reg[2] = root_in_r_reg;
- gpleds_reg[3] = root_in_a;
end
- assign gpleds = gpleds_reg;
-
initial
begin
- gpleds_reg = 0;
root_in_r_reg = 0;
root_in_d_reg = 0;
root_out_a_reg = 0;
- root_in_r_reg = 0;
- read_enable_reg = 0;
- read_reg = 0;
- read_in = 255;
+ data_to_fleet_read_enable_reg = 0;
+ data_to_host_write_enable_reg = 0;
end
-
- // IO buffers
- OBUF obuf_cclk( .I( CCLK_int ),
- .O( CCLK )
- );
-
- IOBUF iobuf_d0( .I( D_O[0] ),
- .IO( D[0] ),
- .O( D_I[0] ),
- .T( D_T[0] )
- );
-
- IOBUF iobuf_d1( .I( D_O[1] ),
- .IO( D[1] ),
- .O( D_I[1] ),
- .T( D_T[1] )
- );
-
- IOBUF iobuf_d2( .I( D_O[2] ),
- .IO( D[2] ),
- .O( D_I[2] ),
- .T( D_T[2] )
- );
-
- IOBUF iobuf_d3( .I( D_O[3] ),
- .IO( D[3] ),
- .O( D_I[3] ),
- .T( D_T[3] )
- );
-
- IOBUF iobuf_d4( .I( D_O[4] ),
- .IO( D[4] ),
- .O( D_I[4] ),
- .T( D_T[4] )
- );
-
- IOBUF iobuf_d5( .I( D_O[5] ),
- .IO( D[5] ),
- .O( D_I[5] ),
- .T( D_T[5] )
- );
-
- IOBUF iobuf_d6( .I( D_O[6] ),
- .IO( D[6] ),
- .O( D_I[6] ),
- .T( D_T[6] )
- );
-
- IOBUF iobuf_d7( .I( D_O[7] ),
- .IO( D[7] ),
- .O( D_I[7] ),
- .T( D_T[7] )
- );
-
- // Clock buffer and reset
- IBUFGDS_LVDS_25 diff_usrclk_buf( .I( Clkin_p ),
- .IB( Clkin_m ),
- .O( User_Clk )
- );
-
- wire [0:3] rst;
-
- FD rst0( .D( 1'b0 ),
- .Q( rst[0] ),
- .C( User_Clk )
- );
- defparam rst0.INIT = 1'b1;
-
- FD rst1( .D( rst[0] ),
- .Q( rst[1] ),
- .C( User_Clk )
- );
- defparam rst1.INIT = 1'b1;
-
- FD rst2( .D( rst[1] ),
- .Q( rst[2] ),
- .C( User_Clk )
- );
- defparam rst2.INIT = 1'b1;
-
- FD rst3( .D( rst[2] ),
- .Q( rst[3] ),
- .C( User_Clk )
- );
- defparam rst3.INIT = 1'b1;
-
- assign User_Rst = |rst;
+endmodule
- // FIFO module instantiation
- user_fifo test_fifo(
- .WrFifo_Din( write_data ),
- .WrFifo_WrEn( write_enable ),
- .WrFifo_Full( write_full ),
- .WrFifo_WrCnt( ),
- .RdFifo_Dout( read_data ),
- .RdFifo_RdEn( read_enable ),
- .RdFifo_Empty( read_empty ),
- .RdFifo_RdCnt( ),
- .User_Rst( User_Rst ),
- .User_Clk( User_Clk ),
- .Sys_Rst( User_Rst ),
- .Sys_Clk( User_Clk ),
- .D_I( D_I ),
- .D_O( D_O ),
- .D_T( D_T ),
- .RDWR_B( RDWR_B ),
- .CS_B( CS_B ),
- .INIT_B( INIT_B ),
- .CCLK( CCLK_int )
- );
-
-endmodule
projects / fleet.git / blobdiff