wire break_o;
wire break;
reg break_last;
+ reg send_k; initial send_k = 0;
wire rst;
assign rst = sys_rst_pin;
break_o,
break);
+ // break and break_o are _active high_
always @(posedge clk) break_last <= break_o;
- assign break = break_o && !break_last;
+ assign break = break_o && !break_last;
+ assign break_done = !break_o && break_last;
reg data_to_host_write_enable_reg;
reg data_to_fleet_read_enable_reg;
data_to_host_write_enable_reg = 0;
/*
if (break) begin
- data_to_host_write_enable_reg = 1;
- data_to_host_r <= 98;
- end else
+ root_out_a_reg = 0;
+ data_to_host_write_enable_reg <= 0;
+/*
+ end else if (break_done) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= 111;
+ send_k <= 1;
+ end else if (send_k) begin
+ data_to_host_write_enable_reg <= 1;
+ data_to_host_r <= 107;
+ send_k <= 0;
*/
if (root_out_r && !root_out_a_reg && !data_to_host_full) begin
data_to_host_write_enable_reg = 1;