module `MODULE_NAME(clk, rst,
in_r, in_a_, in_d,
out_r_, out_a, out_d_);
- input clk;
+ input clk;
input rst;
input in_r;
output in_a_;
reg[3:0] addr;
initial addr = 4'b1111;
+ reg inchead;
+ reg inctail;
+ reg[3:0] count;
+
genvar j;
generate
for(j=0; j<`WIDTH ; j=j+1) begin : OUTX
.A1 (addr[1]),
.A2 (addr[2]),
.A3 (addr[3]),
- .CE (in_r && !in_a && !control[0]),
+ .CE (in_r && !in_a && !control[0] && count==0),
.CLK (clk),
.D (in_d[j]));
defparam SRL16E.INIT = 0;
assign controlx[(1<<`ADDR_BITS)-1] =
!control[(1<<`ADDR_BITS)-1] ? control[(1<<`ADDR_BITS)-2] : (!out_r && !out_a) ? 0 : control[(1<<`ADDR_BITS)-1];
- reg inchead;
- reg inctail;
-
always @(posedge clk) begin
if (rst) begin
out_r <= 0;
in_a <= 0;
control <= 0;
addr <= 4'b1111;
+
+ end else if (count!=0) begin
+ count <= count-1;
+
end else begin
+
+ count <= `DELAY;
+
inchead = 0;
inctail = 0;
if (!in_r && in_a) in_a <= 0;