=> get rid of getInputPort(String) and instead use members
=> get rid of addcrap
=> automatic width-setting/checking on ports
+=> mangle the names given for strings
*/
public class Verilog {
+ public static class PercolatedPort {
+ public static enum PortType { UP, DOWN, INOUT };
+ public final String name;
+ public final int width;
+ public final PortType type;
+ public PercolatedPort(String name, int width, PortType type) {
+ this.name = name;
+ this.width = width;
+ this.type = type;
+ }
+ }
+
public static class SimpleValue implements Value {
public final String s;
public SimpleValue(String s) { this.s = s; }
public String getName() { return name; }
public Port getPort(String name) { return ports.get(name); }
- public HashSet<InstantiatedModule> instantiatedModules = new HashSet<InstantiatedModule>();
+ // order matters here
+ public LinkedList<InstantiatedModule> instantiatedModules = new LinkedList<InstantiatedModule>();
+
+ // order matters here
+ public LinkedList<PercolatedPort> percolatedPorts = new LinkedList<PercolatedPort>();
public final ArrayList<Event> events = new ArrayList<Event>();
// FIXME: always-alphabetical convention?
pw.println(" " + module.getName() + " " + getName() + "(clk, rst ");
for(String s : module.portorder)
pw.println(", " + getPort(s).getSimpleInterface());
- if (module.name.equals("dram")) {
- pw.println(" , dram_addr");
- pw.println(" , dram_addr_r");
- pw.println(" , dram_addr_a");
- pw.println(" , dram_isread");
- pw.println(" , dram_write_data");
- pw.println(" , dram_write_data_push");
- pw.println(" , dram_write_data_full");
- pw.println(" , dram_read_data");
- pw.println(" , dram_read_data_pop");
- pw.println(" , dram_read_data_empty");
- pw.println(" , dram_read_data_latency");
- }
- if (module.name.equals("ddr2")) {
- pw.println(" , ddr2_addr");
- pw.println(" , ddr2_addr_r");
- pw.println(" , ddr2_addr_a");
- pw.println(" , ddr2_isread");
- pw.println(" , ddr2_write_data");
- pw.println(" , ddr2_write_data_push");
- pw.println(" , ddr2_write_data_full");
- pw.println(" , ddr2_read_data");
- pw.println(" , ddr2_read_data_pop");
- pw.println(" , ddr2_read_data_empty");
- pw.println(" , ddr2_read_data_latency");
- }
- if (module.name.equals("video")) {
- pw.println(" , vga_clk");
- pw.println(" , vga_psave");
- pw.println(" , vga_hsync");
- pw.println(" , vga_vsync");
- pw.println(" , vga_sync");
- pw.println(" , vga_blank");
- pw.println(" , vga_r");
- pw.println(" , vga_g");
- pw.println(" , vga_b");
- pw.println(" , vga_clkout");
- }
+ for(PercolatedPort pp : module.percolatedPorts)
+ pw.println(" , "+pp.name);
pw.println(" );");
}
public Port getPort(String name) {
}
public void dump(PrintWriter pw, boolean fix) {
- pw.println("module "+name+"(clk, rst ");
+ boolean isRoot = name.equals("main");
+ pw.print("module "+name);
+ if (isRoot) {
+ pw.println("(clk_pin, rst_pin ");
+ } else {
+ pw.println("(clk, rst ");
+ }
for(String name : portorder) {
Port p = ports.get(name);
pw.println(" , " + p.getInterface());
}
- if (this.name.equals("root")) {
- pw.println(" , dram_addr");
- pw.println(" , dram_addr_r");
- pw.println(" , dram_addr_a");
- pw.println(" , dram_isread");
- pw.println(" , dram_write_data");
- pw.println(" , dram_write_data_push");
- pw.println(" , dram_write_data_full");
- pw.println(" , dram_read_data");
- pw.println(" , dram_read_data_pop");
- pw.println(" , dram_read_data_empty");
- pw.println(" , dram_read_data_latency");
- pw.println(" , vga_clk");
- pw.println(" , vga_psave");
- pw.println(" , vga_hsync");
- pw.println(" , vga_vsync");
- pw.println(" , vga_sync");
- pw.println(" , vga_blank");
- pw.println(" , vga_r");
- pw.println(" , vga_g");
- pw.println(" , vga_b");
- pw.println(" , vga_clkout");
- pw.println(" , ddr2_addr");
- pw.println(" , ddr2_addr_r");
- pw.println(" , ddr2_addr_a");
- pw.println(" , ddr2_isread");
- pw.println(" , ddr2_write_data");
- pw.println(" , ddr2_write_data_push");
- pw.println(" , ddr2_write_data_full");
- pw.println(" , ddr2_read_data");
- pw.println(" , ddr2_read_data_pop");
- pw.println(" , ddr2_read_data_empty");
- pw.println(" , ddr2_read_data_latency");
- }
+ for (InstantiatedModule im : this.instantiatedModules)
+ for(PercolatedPort pp : im.module.percolatedPorts)
+ if (!isRoot || (!pp.name.startsWith("root_in_") && !pp.name.startsWith("rst_")))
+ pw.println(" , "+pp.name);
pw.println(" );");
pw.println();
- pw.println(" input clk;");
- pw.println(" input rst;");
- if (this.name.equals("root")) {
- pw.println("output [31:0] dram_addr;");
- pw.println("output dram_addr_r;");
- pw.println("input dram_addr_a;");
- pw.println("output dram_isread;");
- pw.println("output [63:0] dram_write_data;");
- pw.println("output dram_write_data_push;");
- pw.println("input dram_write_data_full;");
- pw.println("input [63:0] dram_read_data;");
- pw.println("output dram_read_data_pop;");
- pw.println("input dram_read_data_empty;");
- pw.println("input [1:0] dram_read_data_latency;");
- pw.println("output [31:0] ddr2_addr;");
- pw.println("output ddr2_addr_r;");
- pw.println("input ddr2_addr_a;");
- pw.println("output ddr2_isread;");
- pw.println("output [63:0] ddr2_write_data;");
- pw.println("output ddr2_write_data_push;");
- pw.println("input ddr2_write_data_full;");
- pw.println("input [63:0] ddr2_read_data;");
- pw.println("output ddr2_read_data_pop;");
- pw.println("input ddr2_read_data_empty;");
- pw.println("input [1:0] ddr2_read_data_latency;");
- pw.println("input vga_clk;");
- pw.println("output vga_psave;");
- pw.println("output vga_hsync;");
- pw.println("output vga_vsync;");
- pw.println("output vga_sync;");
- pw.println("output vga_blank;");
- pw.println("output [7:0] vga_r;");
- pw.println("output [7:0] vga_g;");
- pw.println("output [7:0] vga_b;");
- pw.println("output vga_clkout;");
+
+ if (isRoot) {
+ pw.println(" input clk_pin;");
+ pw.println(" input rst_pin;");
+ pw.println(" wire clk;");
+ pw.println(" wire clk_fb;");
+ pw.println(" wire clk_unbuffered;");
+ pw.println(" BUFG GBUF_FOR_MUX_CLOCK (.I(clk_unbuffered), .O(clk));");
+ pw.println(" DCM");
+ pw.println(" #(");
+ pw.println(" .CLKFX_MULTIPLY(4),");
+ pw.println(" .CLKFX_DIVIDE(8),");
+ pw.println(" .CLKIN_PERIOD(\"10 ns\")");
+ pw.println(" ) mydcm(");
+ pw.println(" .CLKIN (clk_pin),");
+ pw.println(" .CLKFB(clk_fb),");
+ pw.println(" .CLKFX (clk_unbuffered),");
+ pw.println(" .CLK0 (clk_fb)");
+ pw.println(" );");
+ pw.println(" wire rst;");
+ } else {
+ pw.println(" input clk;");
+ pw.println(" input rst;");
+ }
+
+ for (InstantiatedModule im : this.instantiatedModules)
+ for(PercolatedPort pp : im.module.percolatedPorts) {
+ if (isRoot && (pp.name.startsWith("root_in_") || pp.name.startsWith("rst_")))
+ pw.print("wire");
+ else switch(pp.type) {
+ case UP: pw.print("output"); break;
+ case DOWN: pw.print("input"); break;
+ case INOUT: pw.print("inout"); break;
+ }
+ pw.print(" ");
+ if (pp.width > 1)
+ pw.print("["+(pp.width-1)+":0]");
+ pw.print(" ");
+ pw.print(pp.name);
+ pw.println(";");
+ }
+
+ if (isRoot) {
+ pw.println(" assign rst = rst_out;");
+ pw.println(" assign rst_in = rst_pin;");
}
+
for(String name : ports.keySet()) {
Port p = ports.get(name);
pw.println(" " + p.getDeclaration());
projects / fleet.git / blobdiff