performance improvements in Verilog.java

[fleet.git] / src / edu / berkeley / fleet / fpga / verilog / Verilog.java

diff --git a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
index 04985ff..de2bfba 100644 (file)
--- a/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
+++ b/src/edu/berkeley/fleet/fpga/verilog/Verilog.java
@@ -322,25 +322,6 @@ public class Verilog {
         public String getVerilog() { return s; }
     }
 
-    // Percolated Ports //////////////////////////////////////////////////////////////////////////////
-    
-    /**
-     *  A PercolatedPort is a connection to a top-level pin; it is
-     *  propagated up or down the hierarchy
-     */
-    public static class PercolatedPort {
-        public static enum PortType { UP, DOWN, INOUT };
-        public final String name;
-        public final int width;
-        public final PortType type;
-        public PercolatedPort(String name, int width, PortType type) {
-            this.name = name;
-            this.width = width;
-            this.type = type;
-        }
-    }
-
-
     // Module Internals //////////////////////////////////////////////////////////////////////////////
 
     public static class Module {
@@ -348,7 +329,7 @@ public class Verilog {
             PrintWriter pw = new PrintWriter(new OutputStreamWriter(new FileOutputStream(prefix+"/"+name+".v")));
             dump(pw, true);
             pw.flush();
-            for(InstantiatedModule m : instantiatedModules)
+            for(InstantiatedModule m : instantiatedModules.values())
                 m.module.dump(prefix);
         }
         public int id = 0;
@@ -357,7 +338,7 @@ public class Verilog {
         public Port getPort(String name) { return ports.get(name); }
 
         // order matters here
-        public LinkedList<InstantiatedModule> instantiatedModules = new LinkedList<InstantiatedModule>();
+        public LinkedHashMap<String,InstantiatedModule> instantiatedModules = new LinkedHashMap<String,InstantiatedModule>();
 
         // order matters here
         public LinkedList<PercolatedPort> percolatedPorts = new LinkedList<PercolatedPort>();
@@ -624,22 +605,17 @@ public class Verilog {
             public final Module thisModule;
             public final int id;
             public final HashMap<String,Port> ports = new HashMap<String,Port>();
-            public String getName() { return module.getName()+"_"+id; }
+            private final String name;
+            public String getName() { return name; }
             public InstantiatedModule(Module thisModule, Module module) {
                 this.thisModule = thisModule;
                 this.module = module;
                 // CRUDE
                 int id = 0;
-                OUTER: while(true) {
-                    for (InstantiatedModule im : thisModule.instantiatedModules)
-                        if (im.getName().equals(module.getName()+"_"+id)) {
-                            id++;
-                            continue OUTER;
-                        }
-                    break;
-                }
+                while(thisModule.instantiatedModules.get(module.getName()+"_"+id)!=null) id++;
                 this.id = id;
-                thisModule.instantiatedModules.add(this);
+                this.name = module.getName()+"_"+id;
+                thisModule.instantiatedModules.put(this.name, this);
                 for(String s : module.portorder)
                     getPort(s);
             }
@@ -680,7 +656,7 @@ public class Verilog {
             pw.print("module "+name);
             pw.println(isRoot ? "(clk_pin, rst_pin " : "(clk, rst ");
             for(String name : portorder) pw.println("    , " + ports.get(name).getInterface());
-            for (InstantiatedModule im : this.instantiatedModules)
+            for (InstantiatedModule im : this.instantiatedModules.values())
                 for(PercolatedPort pp : im.module.percolatedPorts)
                     if (!isRoot || (!pp.name.startsWith("root_in_") && !pp.name.startsWith("rst_")))
                         pw.println("    , "+pp.name);
@@ -716,7 +692,7 @@ public class Verilog {
                 pw.println("    input rst;");
             }
 
-            for (InstantiatedModule im : this.instantiatedModules)
+            for (InstantiatedModule im : this.instantiatedModules.values())
                 for(PercolatedPort pp : im.module.percolatedPorts) {
                     if (isRoot && (pp.name.startsWith("root_in_") || pp.name.startsWith("rst_")))
                         pw.print("wire");
@@ -744,7 +720,7 @@ public class Verilog {
             for(WireValue wv : wires.values()) wv.dump(pw);
             for(String name : ports.keySet()) pw.println("    " + ports.get(name).getAssignments());
             for(WireValue wv : wires.values()) pw.println("    " + wv.getAssignments());
-            for(InstantiatedModule m : instantiatedModules) m.dump(pw);
+            for(InstantiatedModule m : instantiatedModules.values()) m.dump(pw);
             pw.println("always @(posedge clk) begin");
             pw.println("  if (rst) begin");
             for(Latch l : latches.values()) pw.println(l.getResetCode());